Integrated program verify page buffer

Details Integrated program verify page buffer Integrated program verify page buffer

1997-12-22

1999-05-11

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518523, 36518512, G11C16/06

Patent

active

059034971

ABSTRACT:
A semiconductor memory includes a plurality of memory cells and a corresponding plurality of page buffers. When writing to a selected row of cells, input data is first latched into the page buffers. The cells in the selected row are then programmed according to the data latched within the page buffers. After programming, data stored in the cells is forwarded to the corresponding page buffers. If, for each cell, the data stored in the cell matches the data latched in its corresponding page buffer, the page buffer is reset. The selected row of cells are subsequently re-programmed, whereby only cells corresponding to those page buffers which have not been reset are re-programmed. In this manner, cells properly programmed during the first program operation are not re-programmed during program verify operations.

REFERENCES:
patent: 5666307 (1997-09-01), Chang
patent: 5687116 (1997-11-01), Kowshik et al.
patent: 5687118 (1997-11-01), Chang
patent: 5691939 (1997-11-01), Chang et al.
patent: 5706227 (1998-01-01), Chang et al.
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5801994 (1998-09-01), Chang et al.

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