Integrated processor and programmable data path chip for...

Details Integrated processor and programmable data path chip for... Integrated processor and programmable data path chip for...

2000-05-25

2001-08-28

Coleman, Eric (Department: 2783)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S013000

Reexamination Certificate

active

06282627

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to reconfigurable computing.
STATE OF THE ART
As the cost of increasingly complex integrated circuits continues to fall, systems companies are increasingly embedding RISC processors into non-computer systems. As a result, whereas the bulk of development work used to be in hardware design, now it is in software design. Today, whole applications, such as modems, digital video decompression, and digital telephony, can be done in software if a sufficiently high-performance processor is used. Software development offers greater flexibility and faster time-to-market, helping to offset the decrease in life cycle of today's electronic products. Unfortunately, software is much slower than hardware, and as a result requires very expensive, high-end processors to meet the computational requirements of some of these applications. Field Programmable Gate Arrays (FPGAs) are also being increasingly used because they offer greater flexibility and shorter development cycles than traditional Application Specific Integrated Circuits (ASICs), while providing most of the performance advantages of a dedicated hardware solution. For this reason, companies providing field programmable or embedded processor solutions have been growing very rapidly.
It has long been known in the software industry that typically most of the computation time of any application is spent in a small section of code. A general trend in the industry has been to build software applications, standardize the interfaces to these computationally intensive sections of code, and eventually turn them into dedicated hardware. This approach is being used by many companies to provide chips that do everything from video graphics acceleration to MPEG digital video decompression. The problem with this approach is that dedicated chips generally take one or more years to create and then are good only for their specific tasks. As a result, companies have begun providing complex digital signal processing chips, or DSPs, which can be programmed to perform some of these tasks. DSPs are more flexible than hardware but are less flexible than standard processors for purposes of writing software.
The logical extension of the foregoing trends is to create a chip which is a processor with dedicated hardware that replaces the computationally intensive sections of the application code. In fact, most complex MPEG chips already include a dedicated embedded processor, but are nevertheless not very flexible. Unfortunately, FPGAs, while they provide greater flexibility, are only 5-10% as dense as gate arrays per usable function. Since there are usually many different sections of computationally intensive code that must be executed at different times within any given application, a more efficient way of using the inherently inefficient FPGA logic is to repeatedly load each specific hardware logic function as it is needed, and then replace it with the next function. This technique is referred to as reconfigurable computing, and is being pursued by university researchers as well as FPGA companies such as Xilinx and others. U.S. Pat. No. 5,652,875 describes a “selected instruction set” computer (SISC) CPU implemented in programmable hardware. A related patent is U.S. Pat. No. 5,603,043. Both of these patents are incorporated herein by reference.
One aspect of reconfigurable computing involves configuration memory structures that allow for configuration data to be changed rapidly. An example of a single-bit portion of a conventional configuration memory structure is shown in FIG.
1
. The configuration memory structure may be represented by interconnected tri-state buffers. A data bit is moved within the configuration memory structure by enabling one or more tri-state buffers. Two separate memory planes are indicated, Plane 0 and Plane 1. The contents of Plane 1 may be applied to FPGA logic by enabling buffers
101
and
103
. The contents of Plane 1 and Plane 0 may be exchanged by enabling buffers
101
,
105
and
107
. Plane 0 and Plane 1 may also be written from an external source by enabling buffers
109
and
111
, respectively. The arrangement of
FIG. 6
limits the planes to serial execution and does not allow for sharing of memory planes. In particular, the FPGA contents cannot be recirculated for storage into the underlying memory planes.
Another memory arrangement is described in U.S. Pat. No. 5,246,378, incorporated herein by reference. In accordance with the teachings of this patent, data defining alternate configurations of reconfigurable logic are stored in stored in different, logically separate memories. Selection circuitry, such as multiplexers, selects between outputs of the different memories and causes the selected outputs to be applied to reconfigurable logic. Time-sliced operation is described.
Another aspect of reconfigurable computing involves “wildcarding,” i.e., writing more than one word of configuration memory simultaneously as a result of a single write access, described in U.S. Pat. Nos. 5,500,609 and 5,552,772, both of which are incorporated herein by reference.
Despite the foregoing efforts, there remains a need for a low-cost, high-performance, flexible reconfigurable computing solution. The present invention addresses this need.
SUMMARY OF THE INVENTION
The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A relatively inexpensive reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic, and interfaces between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. Various features of the reconfigurable processor chip enable it to achieve a lower-cost, higher-performance solution than pure processors. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard FPGA. Configuration planes may be shared between ALU functions and bus interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different proportions of ALU functions and bus interconnect. Many different types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and the configurable “hard-wired” functions.


REFERENCES:
patent: 5500609 (1996-03-01), Kean
patent: 5535342 (1996-07-01), Taylor
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5552722 (1996-09-01), Kean
patent: 5583749 (1996-12-01), Tredennick et al.
patent: 5603043 (1997-02-01), Taylor et al.
patent: 5613146 (1997-03-01), Gove et al.
patent: 5617577 (1997-04-01), Barker et al.
patent: 5652875 (1997-07-01), Taylor
patent: 5680634 (1997-10-01), Estes
patent: 5748979 (1998-05-01), Trimberger
patent: 5752006 (1998-05-01), Baxter
patent: 5956518 (1999-09-01), Delton
patent: 5963745 (1999-10-01), Collins
patent: 6023742 (2000-02-01), Ebeling

Affiliated with

Also associated with

Rating

Integrated processor and programmable data path chip for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated processor and programmable data path chip for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated processor and programmable data path chip for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2547971