Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure
Reexamination Certificate
2002-04-25
2004-08-03
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
C257S517000, C257S526000, C257S500000
Reexamination Certificate
active
06770952
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable
BACKGROUND OF THE INVENTION
This invention is in the field of bipolar transistor fabrication, and is more specifically directed to the fabrication of transistors having varying characteristics on a common substrate according to silicon-on-insulator (SOI) technology.
Integrated circuits have utilized bipolar junction transistors for many years, taking advantage of their high gain characteristics to satisfy high performance and high current drive needs. In particular, as is well known in the art, bipolar transistors are especially well-suited for high frequency applications, such as now used in wireless communications.
Silicon-on-insulator (SOI) technology is also well-known in the art as providing important advantages in high-frequency electronic devices. As is fundamental in SOI technology, active devices such as transistors are formed in single-crystal silicon layers formed over an insulator layer, such as a layer of silicon dioxide commonly referred to as buried oxide. The buried oxide layer isolates the active devices from the underlying substrate, effectively eliminating parasitic nonlinear junction capacitances to the substrate and reducing collector-to-substrate capacitances. To the extent that high frequency performance of bulk transistors was limited by substrate capacitance, SOI technology provides significant improvement.
In addition, SOI devices are robust in high voltage applications. The buried oxide layer effectively eliminates any reasonable possibility of junction breakdown to the substrate.
However, it has been observed that those transistor features that facilitate high frequency performance tend to weaken the device from a high bias voltage standpoint, and vice versa. This tradeoff has typically been addressed by separately manufacturing high voltage integrated circuits and high performance integrated circuits, with each integrated circuit having transistors optimized for their particular implementation. This is because the process complexity resulting from integrating both high voltage and high performance devices in the same SOI integrated circuit adds significant cost and exerts manufacturing yield pressure.
This tradeoff will be further described relative to
FIG. 1
, which illustrates a conventional high-performance p-n-p bipolar transistor
2
formed in an SOI device. An n-p-n device would be formed substantially identically as shown in
FIG. 1
, but with opposite doping conductivity types. Indeed, in many applications, complementary bipolar circuits are formed in the same SOI integrated circuit, having both n-p-n and p-n-p devices formed in this manner.
In this example, substrate
4
effectively serves as a support, or handle wafer for the structure. Buried oxide layer
6
and overlying epitaxial layer
8
are formed at a surface of substrate
4
by the conventional techniques of oxygen implantation, wafer bonding, or smart cut techniques. Epitaxial layer
8
is relatively heavily doped p-type in this example, and serves as a buried collector region. In this example, deep trench isolation structure
7
separates individual structures in epitaxial layer
8
, thus isolating buried collectors from one another in the integrated circuit. Another epitaxial layer, including portions
10
,
12
in this example, is then disposed above and in contact with buried layer
8
in selected locations, separated by shallow trench isolation structures
9
. As shown in
FIG. 1
, shallow trench isolation structures
9
are contiguous with deep trench isolation structures
7
in certain locations to isolate individual devices from one another.
Epitaxial layer
10
is doped in various locations in the definition of transistor
2
. In this example, one epitaxial layer portion is heavily doped n-type to serve as collector sinker contact
12
; a still heavier doped region
13
is provided at the surface of sinker
12
, to further improve the ohmic contact to the collector of transistor
2
. Another portion of epitaxial layer is more lightly-doped, either in-situ with its epitaxial formation or by subsequent ion implantation, to form collector region
10
.
Overlying collector region
10
is intrinsic base region
14
. In this example, intrinsic base region
14
may be an n-type doped silicon layer, or an n-type silicon-germanium layer, epitaxially deposited or otherwise formed at the surface of collector region
10
. As known in the art, the use of a silicon-germanium base provides a high performance heterojunction device, while a silicon base provides a lower performance device at lower manufacturing cost. Extrinsic base structures
15
are disposed adjacent intrinsic base region
14
, to provide a location at which electrical contact to the base may be made. Transistor
2
is completed by the formation of extrinsic emitter
16
, which may be a heavily doped p-type element formed of polysilicon, and from which emitter region
17
diffuses. As a result of this construction, in the operation of transistor
2
, collector-emitter current is conducted substantially by region
11
within collector region
10
.
Each of collector contact
13
, extrinsic base region
15
, and emitter electrode
16
, in transistor
2
according to this embodiment of the invention are made further conductive by the formation of self-aligned silicide layers
18
c,
18
b,
18
e,
respectively.
By way of further background, the conventional construction of a bipolar junction transistor is also described in the prior art. U.S. Pat. No. 5,583,059 is an example of such conventional construction.
Referring back to
FIG. 1
, conventional SOI bipolar transistor
2
is contemplated to be a high performance device. The high performance aspect of transistor
2
is evident by the provision of the heterojunction intrinsic base region
14
, as well as by the provision of a heavily-doped buried collector
8
underlying collector region
10
, to provide a low collector resistance in transistor
2
.
However, high performance transistor
2
is somewhat limited by its construction, from a standpoint of both breakdown voltage and performance. As is fundamental in the art and as applied to the example of
FIG. 1
, this collector-emitter breakdown voltage (BVCEO) depends upon the thickness of collector region
10
and upon the doping concentration of region
11
; lighter doping of region
11
, and a thicker collector region
10
, would increase this breakdown voltage. On the other hand, particularly if intrinsic base region
14
is a heterojunction film, the transistor performance is dominated by collector transit time, which undesirably increases with more lightly doped and thicker collector regions. The optimization of bipolar transistor
2
relative to these two countervailing effects necessarily results in a tradeoff of breakdown voltage versus gain. Therefore, as noted above, it is typical for an integrated circuit to include specific transistors that are optimized for high voltage operation, and also specific transistors that are optimized for performance, rather than attempting to arrive at a single device structure that is optimized for both. However, this implementation of both classes of transistor results in an extremely complex process, doubly so in complementary bipolar processes.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a single manufacturing process suitable for producing both high voltage and high performance bipolar transistors in a silicon-on-insulator (SOI) device.
It is a further object of the present invention to provide a high-voltage bipolar transistor structure that is suitable for implementation in such a process.
It is a further object of the present invention to provide such a structure and process in which the definition of the high voltage transistor is tolerant of alignment and other process parameters.
It is a further object of the present invention to provide such a structure and process that does not involve additional processing steps.
It is a further object of th
Babcock Jeffrey A.
Balster Scott G.
Howard Gregory E
Pinto Angelo
Steinmann Phillipp
Brady III Wade James
Nguyen Tuan H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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