Integrated process for fabricating raised, source/drain, short-c

Details Integrated process for fabricating raised, source/drain, short-c Integrated process for fabricating raised, source/drain, short-c

1993-03-09

1994-05-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 34, H01L 21265

Patent

active

053127684

ABSTRACT:
Processes for fabrication of: an N-channel raised source/drain MOSFET transistor; an N-channel and P-channel raised source/drain MOSFET device; and an N-channel raised source/drain MOSFET in conjunction with a DRAM memory cell capacitor. The process deposits a layer of titanium nitride over the N-channel and P-channel source/drain areas which acts as a barrier to phosphorus or boron atom outdiffusion so that the junction doping levels remain low in the source/ drain areas, and N-channel and P-channel junctions will be shallow. The titanium nitride layer will serve as a dopant atom barrier in a capacitor storage node, an N-channel source/drain area, and a P-channel source/drain area.

REFERENCES:
patent: 5057447 (1991-10-01), Paterson
patent: 5153145 (1992-10-01), Lee et al.
patent: 5168073 (1992-12-01), Gonzalez et al.
Tasch, A. F.; H. Shin; and C. M. Maziar, New Submicron MOSFET Structural Concept For Suppression Of Hot Carriers, Electronics Letters, Jan. 4th, 1990, vol. 26, No. 1, pp. 39-41.

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