Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2002-05-15
2003-11-04
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S007000, C438S785000, C356S369000
Reexamination Certificate
active
06642066
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of a dielectric material film for use in semiconductor devices.
BACKGROUND ART
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and employs film formation, ion implantation, photolithography, etching and deposition techniques to form various structural features in or on a semiconductor substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, usually referred to as a gate oxide, and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide films have served as an impetus for the development of newer, high dielectric constant K (“high-K”) materials as substitutes for conventional silicon dioxide-based gate oxide films. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown field and reliability.
Decreasing the thickness of the gate oxide film between the gate electrode and the source/drain extension regions, together with the relatively high electric field across the gate oxide film, can undesirably cause charge carriers to tunnel across the gate oxide film.
This renders the transistor “leaky”, degrading its performance. To alleviate this problem, high-K dielectric materials are used as the gate insulator. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material film, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide.
Using a high-K dielectric material for the gate dielectric film provides a low electrical thickness to be achieved while retaining a physically thick film. For example, a high-K gate dielectric with a K of 40 and a thickness of 100 angstroms is substantially electrically equivalent to a silicon dioxide gate dielectric (K about 4) having a thickness of about 10 angstroms. The electrically equivalent thickness of high-K materials may be referred to in terms of the equivalent oxide thickness of a film of silicon dioxide. Thus, a high-K dielectric film having K value of 40 and a given physical thickness has an equivalent oxide thickness which is approximately {fraction (1/10)} the given physical thickness. For higher-K dielectric materials, even thicker gate dielectric material films can be formed while maintaining equivalent oxide thickness values lower than are reliably and practically possible with very thin silicon dioxide films. In this way, the reliability problems associated with very thin dielectric films may be avoided while transistor performance is increased.
High-K dielectric materials may be used in many semiconductor devices, including for example, SONOS-type devices such as the MIRRORBIT™ flash memory cell available from Advanced Micro Devices, Inc., Sunnyvale, Calif., and in floating gate flash memory cells.
One problem which has been encountered in fabricating semiconductor devices including high-K dielectric materials is dimensional control, particularly being able to obtain a desired thickness and a desired K value of high-K dielectric materials. Since obtaining a given equivalent oxide thickness depends upon both the physical thickness and the K value of the dielectric material, control of these parameters is needed. It would be highly advantageous to develop a process that would permit close control of the thickness of high-K dielectric material films which are applied in semiconductor devices, and for this control to be available during the deposition of the dielectric material films, i.e., in situ. In addition, it is advantageous to develop methodologies capable of optimum fabrication processes for such devices. Accordingly, there exists a need for a process of manufacturing semiconductor devices with a high-K dielectric material film that improves process control of the quality, thickness and K value of dielectric material films, and particularly in high-K dielectric material films, while avoiding unduly expensive and time-consuming post-process physical measurement and/or electrical testing of such dielectric films.
DISCLOSURE OF INVENTION
The present invention relates to a method of depositing a dielectric material film, including steps of initiating a process of depositing a dielectric material film under at least one controllable initial condition in an apparatus comprising a dielectric material deposition chamber and a spectroscopic ellipsometer; and measuring in situ, by the spectroscopic ellipsometer, at least one ellipsometric parameter of the dielectric material film during the process of depositing the film.
In another embodiment, the present invention relates to a process for depositing a high-K dielectric material on a semiconductor substrate, including steps of providing an apparatus comprising both a device for depositing a dielectric material and a device configured to measure in situ at least one ellipsometric parameter relating to at least one of refractive index and dielectric constant of the dielectric material; placing a semiconductor substrate into the apparatus; depositing on the semiconductor substrate a film comprising a high-K dielectric material; measuring, during the depositing step, the ellipsometric parameter relating to at least one of refractive index and dielectric constant of the dielectric material film; and controlling, during the depositing step, at least one process parameter relating to the depositing step based on the ellipsometric parameter relating to at least one of refractive index and dielectric constant of the dielectric material film.
In one embodiment, the present invention relates to an apparatus including a first device for depositing a dielectric material; a second device configured to measure in situ at least one ellipsometric parameter relating to at least one of refractive index and dielectric constant of the dielectric material during deposition of the dielectric material in the first device; a processor for receiving the at least one ellipsometric parameter from the second device and outputting information relating to at least one process parameter; and a controller for receiving information from the processor and adjusting operating conditions of the first device based on the information relating to the at least one process parameter. The apparatus may be used to carry out the methods of the present invention.
The present invention, while primarily for use with high-K dielectric materials, is broadly applicable to deposition of any dielectric mater
Arsania Farzad
Halliyal Arvind
Advanced Micro Devices , Inc.
Ghyka Alexander
Renner , Otto, Boisselle & Sklar, LLP
LandOfFree
Integrated process for depositing layer of high-K dielectric... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated process for depositing layer of high-K dielectric..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated process for depositing layer of high-K dielectric... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3147075