Integrated pre-adder for a multiplier

Details Integrated pre-adder for a multiplier Integrated pre-adder for a multiplier

1996-11-19

1998-11-10

Sheikh, Ayaz R.

Boots, shoes, and leggings

36473602, 36474807, 3647505, 36475401, 364757, 364759, 36476001, 36476002, 36476005, G06F 752

Patent

active

058353933

ABSTRACT:
A preadder for a multiplier integrates a pre-adder and Booth encoder. The integrated pre-adder/Booth encoder comprises multiple stages, each of which adds and encodes multiple bits (usually two) of two numbers x and y. Each stage comprises three blocks, a first carry generation block, a second carry generation block, and an output code generation block. The x input bits and y input bits are input into the first carry block, which generates a first carry out and multibit combination signal, which generally comprises the x input bits and y input bits carried straight through or only slightly modified. The combination signal and a first carry in signal are inputs to the second carry generation block. Generally, the first carry in is the is the first carry out of another stage which is combining less significant bits than the present stage. The second carry generation block generates a second carry out signal and a sum signal. The sum signal generally comprises bits of x added or otherwise combined with bits of y. The sum signal and a second carry in signal are inputs to the code generation block. Generally, the second carry in signal is the second carry out signal of another stage which is adding less significant bits. The code generation block generates the Booth code of the sum signal, accounting for the second carry in signal.

REFERENCES:
patent: 4546446 (1985-10-01), Machida
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4864528 (1989-09-01), Nishiyama et al.
patent: 5262976 (1993-11-01), Young et al.
Weste, Neil H.E., and Kamran Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, Chapter 8, "Subsystem Design: Datapath Operators," Addison-Wesley Publishing Company (1993), pp. 545-554.
Vaidyanathan, P.P., Multirate Systems and Filter Banks, Part 2, Chapter 5, "Multirate Filter Banks: Maximally Decimated Filter Banks," Prentice Hall, pp. 188-285.

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