Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Patent
1993-07-08
1995-05-09
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
257 67, 257109, 257133, 257378, 257379, H01L 2900, H01L 2702
Patent
active
054133130
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
The present invention refers to an integrated power switch structure, which comprises a lateral or a vertical thyristor controlled by a lateral MOS gate and wherein said lateral MOS gate has its drain-source path connected in series with the cathode-anode path of the thyristor according to the generic clause of claim 1.
The present invention deals, in general, with the improvement of a power switch structure which is suitable for switching high loads.
For switching high loads, power DMOS transistors are regarded as being ideal switching elements for the range of low voltages of less than 100 V even in the case of high currents exceeding 10 A. A power DMOS transistor has a low resistance in the switched-on condition and it permits rapid switching on and off. When higher voltages in the range between 500 V and 1500 V are used, the product of the switch-on resistance and the area, which is an important measure of the quality of the component, will increase more and more and become, consequently, more and more disadvantageous in the case of power DMOS transistors.
On the basis of a known power DMOS transistor, which is designated generally by reference numeral 50 in FIG. 5, the reason for the fact that the quality of the component will deteriorate when higher voltages are to be switched will be explained hereinbelow. As can be seen from the figure, such a DMOS transistor 50 comprises a gate 51, a source electrode 52 and a drain electrode 53, which borders on an n.sup.+ -substrate 54. The known power DMOS transistor 50 includes at each source-electrode region 52 an n.sup.+ -region 55, which is enclosed by a p-base region 56. An n-drift region 58 is located between the n.sup.+ -substrate 54 and the p-base regions 56, said n-drift region being defined by a lightly doped semiconductor layer formed by epitaxial growth on the high-doped n.sup.+ -silicon substrate 54. The dielectric strength of the known DMOS transistor 50 is adjusted via the space-charge zone of a pn-junction extending into the semiconductor layer 58 which has been formed by epitaxial growth. The further the space-charge zone can spread, i.e. the larger the semiconductor layer 58 formed by epitaxial growth is and the lower its doping is, the higher is the dielectric strength of the DMOS transistor 50. On the other hand, the switch-on resistance will increase when the drift distance becomes larger and when the doping becomes lower, since the current has to pass through the layer 58 formed by epitaxial growth.
In order to reduce the epitaxial resistance, a socalled IGBT (Insulated Gate Bipolar Transistor) or IGT, which is shown in FIG. 6 and which is designated generally by reference numeral 60, is used in field of power electronics. With the exception of the differences explained hereinbelow, the structural design of such a transistor corresponds to that of the DMOS transistor 50 which has been explained with regard to FIG. 5, identical parts and regions being designated by like reference numerals. In the case of the IGBT 60 according to FIG. 6, the n.sup.+ -substrate 54 of the DMOS transistor 50 according to FIG. 5 has been replaced by a p.sup.+ -substrate 64 which is doped just as highly. The resultant pn-junction between the substrate 64 and the layer 58 formed by epitaxial growth is, in the switched-on condition polarized in the forward direction, connected in series with the actual transistor and injects a large number of minority carriers, i.e. holes, into the layer 58 formed by epitaxial growth. This will have the effect that the resistance of said layer 58 is reduced drastically by one to two orders of magnitude in comparison with the epitaxial resistance of the DMOS transistor 50 according to FIG. 5. It is, however, necessary to limit the charge carrier injection, since, otherwise, a parasitic p.sup.+ n.sup.- pn.sup.+ -transistor will fire so that the current through the IGBT 60 can no longer be controlled by the MOS gate 51. This control has the advantage that it is effected capacitively via an insulating layer 59 and that, con
REFERENCES:
patent: 4847671 (1989-07-01), Pattanayak
B. J. Baliga, Electron Device Letters, vol. 20, 1990, "The MOS-Gated Emit Switched Thyristor," pp. 75-77.
B. J. Baliga, Solid State Electronics, vol. 25, 1982, "High Gain Power Switching Using Field Controlled Thyristors," pp. 345-353.
W. Seifert, A. A. Jaecklin, IEEE Trans. Elec. Dev., vol. 34, 1987, "An FET-Driven Power Thyristor," pp. 1170-1176.
Mutterlein Bernward
Vogt Holger
Dougherty Ralph H.
Fraunhofer-Gesellschaft zur Forderung der ange-wandten Forschung
Ngo Ngan V.
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