Patent
1989-12-19
1992-06-02
Mintel, William
357 234, 357 2313, 357 42, H01L 2702
Patent
active
051191628
ABSTRACT:
Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).
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Andreini, et al., "A new Integrated Silicon Gate Technology Combining Bipolar-Linear, CMOS Logic, and DMOS Power Parts," IEEE Trans. vol. 33, No. 12, pp. 2025-2030, Dec. 1986.
Sun et al., "Modeling of the On-Resistance of LDMOS, VDMOS and VMOS Power Transistors", IEEE Trans., vol. 27, No. 2, Feb. 1980, pp. 356-358.
Fong et al, "Power DMOS for High-Frequency and Switching Applications," IEEE Trans, Vol, 27, No. 2, Feb. 1980, 322-325.
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Cotton David R.
Efland Taylor R.
Jones, III Roy C.
Lee John K.
Todd James R.
Donaldson Richard
Hiller William E.
Honeycutt Gary C.
Mintel William
Potter Roy
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