Integrated power devices and signal isolation structure

Details Integrated power devices and signal isolation structure Integrated power devices and signal isolation structure

2006-11-14

2006-11-14

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

Reexamination Certificate

active

07135766

ABSTRACT:
A flip chip power device having an integrated low inductance ground and heat sink path and an isolation structure is provided. A substrate is formed having transistors and an ohmic contact region circumscribing the transistors. Dielectric layers are formed on the substrate, and a common metal layer is formed on the dielectric layers. An isolation metal layer is formed on the dielectric layers above the ohmic contact region. The common metal layer is coupled to a first region of each of the transistors, and the isolation metal layer is coupled to the ohmic contact region. A first bump is formed on the common metal layer, and a second bump is formed on the isolation metal layer. When the power device is attached to a second substrate, the first bump forms a low inductance ground and heat sink path to the second substrate, and an isolation structure is formed.

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