Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Including additional component in same – non-isolated structure
Reexamination Certificate
2002-01-04
2004-09-07
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Including additional component in same, non-isolated structure
C257S133000, C257S135000, C257S140000, C257S146000
Reexamination Certificate
active
06787881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention refers to an integrated power device, and more particularly to an IGBT with control circuit having improved efficiency and reduced overall dimensions.
2. Description of the Related Art
As is known, power devices are used in all applications that require handling of high voltages and currents.
For example,
FIG. 1
shows an integrated power device
1
comprising a power transistor
2
, built using an insulated-gate bipolar transistor (IGBT), and a control circuit, which may, for example, be made as described in the European patent application No. 00830051.9 filed on Jan. 27, 2000 in the name of the present applicant. More specifically, the power transistor
2
has a collector terminal on which a high collector voltage Vc (for example 300 to 400 V) is present, an emitter terminal connected to a ground line GND set at a ground voltage V
GND
, and a control terminal connected to an output terminal
3
a
of the control circuit
3
.
In turn, the control circuit
3
comprises an input terminal
3
b
for receiving a driving signal S, a supply terminal
3
c
set at a supply voltage VB (for example, of from 6 to 24 V), a ground terminal
3
d
connected to the ground line GND, a sensing terminal
3
e
connected to the collector terminal of the power transistor
2
, and a feedback terminal
3
f
connected to the emitter terminal of the power transistor
2
via a voltage-to-current transducer
4
.
The control circuit
3
receives the driving signal S and controls turning-on and turning-off of the integrated power device
1
. In addition, it carries out a control on the value of the collector voltage Vc, detected by the sensing terminal
3
e
, for example by blocking the collector voltage Vc at a value programmed according to the operating conditions of the integrated power device
1
, or else by stabilizing the oscillations of the collector voltage Vc during transients, or yet again by controlling the value dVc/dt. The control circuit
3
also controls the value of the current Ic flowing in the power transistor
2
. The current Ic is detected by the voltage-to-current transducer
4
, which supplies it to the control circuit
3
via the feedback terminal
3
f
. In this case, the control circuit
3
carries out a control on the current Ic, for example by controlling the value dIc/dt, or else by preventing the current Ic from exceeding a maximum value beyond which the integrated power device
1
may be subject to failure.
At present, there exist two possible solutions for assembling the integrated power device
1
described above.
In a first solution (chip-to-chip solution), shown in
FIG. 2
, a first chip
60
and a second chip
61
, which respectively integrate the power transistor
2
and the control circuit
3
(of which
FIG. 2
shows only one portion), are soldered on one and the same copper plate
5
. In this first solution, the control circuit
3
is made using an M1-type technology, which enables integration, in a high-voltage region (i.e., one able to withstand high voltages, for example 500 V), of components operating at low voltages (for example, 40 V).
In greater detail, the first chip
60
comprises a first substrate
6
, of the P type, soldered on a first portion
5
a
of the copper plate
5
and defining a collector region of the power transistor
2
. A first epitaxial layer
7
, of the N
+
type, is grown on top of the first substrate
6
, and a second epitaxial layer
8
, of the N
−
type, and having a surface
8
a
, is grown on top of the first epitaxial layer
7
. Body regions
9
, of the P
+
type, are housed in the second epitaxial layer
8
, are set facing the surface
8
a
, and in turn house emitter regions
10
, of the N
+
type, set apart from one another by means of respective portions
9
a
of the body regions
9
.
Polysilicon gate regions are set between pairs of body regions
9
, on top of the surface
8
a
, and are electrically insulated from the latter by a gate-oxide layer
12
. A thick oxide layer
13
envelops the gate regions
11
and separates them electrically from a metal emitter-contact region
14
, which extends on top of the chip
60
and is in electrical contact with the emitter regions
10
and with the portions
9
a
of the body region
9
by means of contact portions
14
a.
The second epitaxial layer
8
also houses an edge structure
15
of the power transistor
2
comprising a first annular region
16
, a second annular region
19
, and an equipotential portion
8
′ belonging to the second epitaxial layer
8
and facing the first annular region
16
and the second annular region
19
. The first annular region
16
, of the P
−
type, completely surrounds the area in which the body regions
9
are formed (active area
17
) and is overlaid by a thick field-oxide layer
18
. The second annular region
19
, of the N
+
type, surrounds the first annular region
16
externally (
FIG. 3
) and forms a channel stopper.
A field-plate region
20
extends on top of the active area
17
and is electrically insulated from the surface
8
a
of the second epitaxial layer
8
by the gate-oxide layer
12
. A Zener diode
21
extends in part over the field-oxide layer
18
adjacent to the field-plate region
20
. The field-plate region
20
and the Zener diode
21
are formed starting from one and the same polycrystalline-silicon layer.
The Zener diode
21
has a first end
21
a
and a second end
21
b
. The first end
21
a
is in electrical contact with a metal gate-contact region
22
, which is set outside the active area
17
(FIG.
3
), whilst the second end
21
b
is in electrical contact with a first contact portion
23
a
of a metallization region
23
. The metallization region
23
has a second contact portion
23
b
which is in electrical contact with the equipotential portion
8
′, as schematically represented in
FIG. 2
, via an intermediate node
24
connected to the collector region
6
through a first diode
25
, and to the metal emitter-contact region
14
through a second diode
26
.
In particular, the first diode
25
has a cathode region defined by the first epitaxial layer
7
and an anode region defined by the collector region
6
, whilst the second diode
26
has an anode region defined by the body region
9
and a cathode region defined by the epitaxial layer
8
. The first diode
25
and the second diode
26
are connected together in antiseries via the intermediate node
24
.
The second chip
61
comprises a high-voltage region
30
which is bonded on top of a second portion
5
b
of the copper plate
5
, adjacent to the first portion
5
a
. The high-voltage region
30
is electrically connected to the collector region
6
of the power transistor
2
by means of the copper plate
5
and is formed by a second substrate
31
, of the N
+
type, directly bonded on the second portion
5
b
of the copper plate
5
, and a third epitaxial layer
32
, of the N
−
type, grown on top of the second substrate
31
and having a surface
32
a
. The third epitaxial layer
32
houses an insulation region
33
, of the P type, delimiting a first portion
32
b
and a second portion
32
c
of the third epitaxial layer
32
, in which a first bipolar transistor
34
, of the PNP type, and a second bipolar transistor, of the NPN type, which operate at low voltage, are respectively made.
More specifically, the first bipolar transistor
34
comprises a buried base region
36
, of the N
+
type, formed on top of the isolation region
33
and extending in part into the latter, and a deep base region
37
, also of the N
+
type, which extends from the surface
32
a
of the third epitaxial layer
32
as far as the buried base region
36
so as to connect the latter electrically to the surface
32
a
itself. Above the buried base region
36
and at a distance from the latter are a first surface region
38
, a second surface region
39
, and a third surface region
40
, all of the P type. The first surface region
38
and the third s
Fragapane Leonardo
Letor Romeo
Torres Antonino
Dickey Thomas L
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
LandOfFree
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