Integrated PLL loop filter and charge pump

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

Reexamination Certificate

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C327S157000

Reexamination Certificate

active

07427900

ABSTRACT:
A charge pumped phase locked loop circuit (PLL) is disclosed that includes a phase detector for detecting the phase error between a reference clock and an output clock to generate a phase error signal. A charge pump is provided that is controlled by the phase error signal to either source current to an intermediate control node or to sink current therefrom. An isolation circuit maintains the intermediate control node at a virtual AC reference voltage such that it remains at substantially the same voltage during the sourcing of current thereto or sinking of current therefrom, the isolation circuit generating a control voltage on the output thereof to control the frequency of the output clock. A loop filter is provided for filtering the control voltage.

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patent: 7154345 (2006-12-01), Moyal et al.
David R. Smith, “5.5 Pulse Shaping and Intersymbol Interference,” Digital Transmission Systems, Copyright 1985, pp. 207-210, 562, Van Nostrand Reinhold Company Inc., New York, New York, U.S.A.

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