Integrated plating and planarization process and apparatus...

Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Contacting coating as it forms with solid member or material...

Reexamination Certificate

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C204S212000, C204S22400M, C204S272000, C204S275100, C205S103000, C205S117000, C205S123000, C205S143000, C205S222000, C205S223000, C205S917000

Reexamination Certificate

active

06773570

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor processing, and more particularly to a process and apparatus for plating and planarization of a copper layer on a semiconductor wafer.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor devices, deposition and selective removal of metallic layers are important processes. A typical semiconductor wafer has several layers of metal deposited or plated on its surface, with each successive layer being polished or etched before further layers are added. In particular, electroplating of copper on the wafer surface is a widely practiced process. Plating of copper (which generally produces a blanket layer of copper on the wafer) is typically followed by chemical-mechanical polishing (CMP) to remove unwanted portions of the plated layer. When a damascene structure is being fabricated, the CMP process also serves to electrically isolate the damascene wires.
FIG. 1A
is a schematic illustration of a typical apparatus for plating copper on a wafer. Wafer
1
is held against a cathode
32
by sealed contacts
33
; the cathode and wafer rotate in a bath
30
of plating solution. A flow
35
of plating solution is pumped through the apparatus to continually refresh the bath; the flow is directed around plating anode
31
and through holes in the anode.
FIG. 1B
shows a wafer feature after a typical Cu plating process. Semiconductor wafer
1
, which has a trench
3
formed therein, is coated first with a barrier/liner layer
2
, to promote adhesion of the plated metal layer to the wafer and to prevent diffusion of the Cu into the semiconductor material. A seed layer
4
is then deposited on layer
2
. The electroplated Cu layer
5
fills the trench and coats the wafer surface. As shown in the figure, the plated layer must be thick enough to ensure that the trench is filled. Under some process conditions the greatest thickness is in the vicinity of the trench, as shown in FIG.
1
C. The excess thickness
5
a
, termed “overburden,” is then removed by CMP. Often the entire plated layer above the wafer surface is removed so that copper metal remains only inside the trench
3
; this may be done by polishing the wafer in a CMP apparatus until the original front surface
1
f
of the wafer is exposed.
Plating and planarization of the metal layer are conventionally done in separate tools. As noted above, processing of a typical wafer requires several different plating steps, with each followed by a planarization step. A typical wafer therefore is processed multiple times in both the plating and planarization tools. This situation tends to limit the throughput of the manufacturing process, and accordingly increases the overall manufacturing cost.
U.S. Pat. No. 6,004,880, titled “Method of single step damascene process for deposition and global planarization,” suggests adapting a CMP apparatus to perform plating and polishing simultaneously. However, plating and polishing often require different process conditions (e.g. different mechanical force on the wafer surface), which cannot be obtained in a simultaneous process. Furthermore, if a polishing slurry containing an abrasive is combined with an electrolyte plating solution, abrasive particles may be trapped in the plated metal layer.
U.S. Pat. No. 5,911,619, titled “Apparatus for electrochemical mechanical planarization,” describes a polishing apparatus in which electrodes contact the wafer, so that CMP and electrochemical machining techniques may be combined in order to improve planarization throughput. This apparatus is used only for planarization (that is, removal of material from the wafer); electroplating of the wafer requires a separate apparatus.
There remains a need for a wafer processing tool which integrates the features of electroplating and planarization tools, and thus can perform alternating electroplating and electroetching processes, together with CMP (particularly for copper layers), with optimized conditions for each process.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a process and apparatus for performing both electroplating of a metal layer and planarization of the layer on a substrate.
According to a first aspect of the invention, the apparatus includes a table with a polishing pad; the table and pad have holes therein forming channels for dispensing an electroplating solution onto the pad. A plurality of electroplating anodes are disposed in the channels and are in contact with the electroplating solution. The apparatus also includes a carrier for holding the substrate substantially parallel to the top surface of the pad and for applying variable mechanical force on the substrate against the pad; the carrier rotates with respect to the table and includes a plating cathode. The apparatus further includes a slurry dispenser for dispensing a polishing slurry on the pad during a CMP process.
The carrier applies a first amount of force during an electroplating process and a second amount of force during an electroetching process. During a plating process, it is preferable that the force be varied to maintain a predetermined spacing between the substrate and the pad. In the initial plating process for a dual damascene structure, this spacing should be between 5 &mgr;m and 100 &mgr;m.
The channels are advantageously arranged in a plurality of concentric arrays each having an anode therein, so that the anodes are arranged in concentric arrays each having a separate electrical connection to the cathode.
It is noteworthy that when a conductive line or via is being formed, the first amount of force is greater than the second amount of force, so that the distance between the substrate and the top surface of the pad is greater during an electroetching process than during an electroplating process.
The table and pad may have additional arrays of holes to form channels for dispensing the polishing slurry during the CMP process.
According to another aspect of the invention, a method is provided for performing both electroplating of a metal layer and planarization of the layer on a substrate in an integrated plating/planarization tool having a substrate carrier and a table with a polishing pad disposed thereon. In this method, the substrate is loaded on the carrier, and electroplating solution is dispensed onto the pad. Metal is then electroplated on the substrate using the electroplating solution, while a first amount of mechanical force is applied on the substrate against the pad to maintain a first spacing between the substrate and the pad. An electroetching solution is then dispensed onto the pad, and the metal on the substrate is electroetched, while a second amount of mechanical force is applied on the substrate against the pad to maintain a second spacing between the substrate and the pad. The electroplating and electroetching may be repeated as a sequence a plurality of times. The method may further include the step of polishing the metal by chemical-mechanical polishing (CMP) using the polishing pad and a non-abrasive slurry dispensed on the pad. The table may have a plurality of plating anodes connected thereto and arranged in separate concentric arrays; in the electroplating step, a selected array may be connected to a voltage source so as to control the thickness of the metal plated on the substrate. The electroetching may be performed using the electroplating solution; in this instance, current is conducted between the cathode and the anodes in a forward direction during the electroplating and in a reverse direction during the electroetching.


REFERENCES:
patent: 5911619 (1999-06-01), Uzoh et al.
patent: 6004880 (1999-12-01), Liu et al.
patent: 6270646 (2001-08-01), Walton et al.
patent: 6328872 (2001-12-01), Talieh et al.
patent: 6454916 (2002-09-01), Wang et al.
patent: 6478936 (2002-11-01), Volodarsky et al.
patent: 2003/0183530 (2003-10-01), Chou et al.

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