Radiant energy – With charged particle beam deflection or focussing – Magnetic lens
Reexamination Certificate
2007-02-20
2007-02-20
Wells, Nikita (Department: 2881)
Radiant energy
With charged particle beam deflection or focussing
Magnetic lens
C250S378000, C250S489000
Reexamination Certificate
active
11048229
ABSTRACT:
An apparatus for an ion trap includes an electrically conductive substrate having top and bottom surfaces and having vias that cross from the top surface to the bottom surface. The apparatus includes a pair of planar first electrodes supported over said top surface and second electrodes having planar surfaces. The planar surfaces are located over said top surface, and portions of the planar surfaces are located laterally adjacent to said planar first electrodes. One of the second electrodes includes a portion that is located in one of the vias and traverses the substrate.
REFERENCES:
patent: 5206506 (1993-04-01), Kirchner
patent: 5501893 (1996-03-01), Laermer et al.
patent: 6075263 (2000-06-01), Takahashi et al.
patent: 2005/0040327 (2005-02-01), Lee et al.
U.S. Appl. No. 11/003,823, filed Dec. 3, 2004, Aksyuk et al.
U.S. Appl. No. 10/656,432, filed Sep. 5, 2003, Pai et al.
U.S. Appl. No. 10/780,091, filed Feb. 27, 2004, Pai et al.
Miller, K., et al., “Die-scale wafer flatness: 3-dimensional imaging across 20 mm with nanometer-scale resolution,” SPIE Microlithography, 4689-92, (2002), 5 pages.
McAuley, S.A., et al., “Silicon micromachining using a high-density plasma source,” Journal of Physics D: Applied Physics, vol. 34, pp. 2769-2774, (2001).
Rosen, D., et al., “Membrane covered electrically isolated through-wafer via holes,” Journal of Micromechanics and Microengineering, vol. 11, pp. 344-347, (2001).
Yamada, H., et al., “High-Density 3-D Packaging Technology Based on the Sidewall Interconnection Method and Its Application for CCD Micro-Camera Visual Inspection System,” IEEE Transactions on Advanced Packaging, vol. 26, No. 2, pp. 113-121, (2003).
Wu, J.H., et al., “A Through-Wafer Interconnect in Silicon for RFICs,” IEEE Transactions on Electron Devices, vol. 51, No. 11, pp. 1765-1771, (Nov. 2004).
Kielpinski, D., et al., “Architecture for a large-scale ion-trap quantum computer,” Nature, vol. 417, pp. 709-711, Jun. 13, 2002.
Zhang, Y., et al., “Importance of wafer flatness for CMP and lithography,” SPIE, vol. 3050, pp. 266-269, (1997).
Pau Stanley
Slusher Richart Elliott
McCabe John F.
Quash Anthony
Wells Nikita
LandOfFree
Integrated planar ion traps does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated planar ion traps, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated planar ion traps will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3875805