Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2003-08-28
2004-10-26
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S459000
Reexamination Certificate
active
06809008
ABSTRACT:
The present invention generally relates to semiconductor and imaging devices; and more particularly, to systems and methods for integrating photosensing elements for use in CMOS imaging applications.
CMOS imagers have begun to challenge CCDs in many electronic imaging applications and are gaining in popularity. The primary advantages of CMOS imagers are their relatively low cost generally resulting from the use of standard, high-volume CMOS processes and their ability to be integrated with native CMOS electronics for control and image processing; this in contrast to CCDs, which typically employ specialized processing optimized for image capturing operations that are not generally amenable to large-scale integration of electronics.
Because the photodiodes (PDs) of CMOS imagers are usually fabricated within the same material layer and with similar processes as the electronics, and these materials and processes are often dominated by and optimized for electronic circuitry, the optical and optoelectronic design of the photosensor are generally compromised. Representative limitations involve the Si material itself wherein a fixed band gap generally obstructs the use of band gap engineering as an effective design tool. The material may be responsive to light at visible wavelengths enabling use for many imaging/camera applications, but very weak in the near-IR spectral region where additional applications may exist. Due to the indirect band gap, light absorption may be relatively weak, even at visible wavelengths. Accordingly, thick absorbing layers and deep junctions may be needed to achieve high efficiency; these same design criteria generally being in conflict with those for high performance electronic applications.
Incompatibility between the optoelectronic and electronic requirements may be further exacerbated by current scaling trends—in terms of both the pixel pitch and the progression to smaller critical dimension CMOS process technologies (i.e., technology scaling). As the size of the pixel shrinks to reduce the cost of imaging chips, the illuminated area of the photodetector is also typically reduced thereby decreasing the captured signal level. Moreover, as the photodetector active area is reduced, the dark current becomes dominated by the perimeter causing inter alia the noise current density to increase. Together, these effects generally operate to degrade the signal to noise performance of the sensor.
There is a current trend that involves increasing the amount of electronic circuitry within each pixel from about the 3-4 transistor level for active pixel sensors (APS) to more than about 100 transistors for digital pixel sensors (DPS). This desire for increased signal processing functionality within the pixel escalates competition for ‘real estate’ within the pixel area creating additional problems generally associated with shrinking the PD active area, reducing the fill factor within the pixel, and applying advanced process technologies.
Migration to advanced process technologies may further compromise PD device design and performance. 0.25&mgr; technologies and beyond typically employ suicides that are optically opaque and potentially leaky, as well as shallow trench isolation (STI) which may often lead to higher perimeter-generated dark current levels. Furthermore, reduced lateral dimensions are generally attended by reduced vertical dimensions leading to thinner layers and shallower junctions as well as higher doping levels and reduced carrier diffusion lengths. Reduced supply voltages also may negatively impact charge collection and storage capability of the PD. Moreover, an ever-increasing number of interconnect levels and corresponding isolating dielectric layers generally decreases the optical throughput and coupling efficiency to the photodetector and introduces additional sources of reflection and scattering that can lead to elevated levels of optical crosstalk.
Efforts to improve the level of PD performance can limit flexibility and performance in the CMOS electronics as well. Minimizing the number of interconnect levels to improve the optical coupling to the PD, for example, may make interconnect routing more difficult and less area-efficient.
The co-integration of the photosensor with the CMOS electronics (i.e., within the same material layer, using the same processes, etc.) within the pixel of CMOS imagers may severely limit both the performance of the photosensor and the flexibility of the system architectural design. This problem may be further complicated by progression to more advanced CMOS technology generations which generally utilize trench isolation, non-transparent silicides, and increasing numbers of interconnect levels. The current trend toward increase functionality within the pixel (as with digital pixel sensors—DPS) adds more electronic circuitry within the pixel creating competition for pixel area, decreasing fill factor and further compromising of performance. To allow enhanced optimization of the photosensing and the electronics functions, as well as greater flexibility in architectural design, a new imager platform is needed.
REPRESENTATIVE SUMMARY
In various representative aspects, the present invention provides integrated photosensors for CMOS imagers using 3D integration schemes in which inter alia a monocrystalline active layer is incorporated over and in close proximity to a processed CMOS wafer. The monocrystalline layer may be transferred to the CMOS wafer by means of, for example, wafer-to-wafer (or die-to-wafer) bonding followed by substrate removal. The integrated photosensing layer is sufficiently proximate to the final metallization of the CMOS wafer to provide inter alia a high density of interconnects for electrical contacts. An exemplary method for fabricating such a device is disclosed as comprising the steps of inter alia: providing a processed CMOS wafer; providing a photosensing element fabricated in an integrated optically active layer comprising a monocrystalline material; bonding the optically active layer to the CMOS layer in a region disposed substantially near a metalization surface of the CMOS layer in order to permit fabrication of an interconnect via, wherein the photosensing element is substantially decoupled from the interconnect via.
Additional advantages of the present invention will be set forth in the Detailed Description which follows and may be obvious from the Detailed Description or may be learned by practice of exemplary embodiments of the invention. Still other advantages of the invention may be realized by means of any of the instrumentalities, methods or combinations particularly pointed out in the claims.
REFERENCES:
patent: 2003/0157748 (2003-08-01), Kim et al.
patent: 2004/0041178 (2004-03-01), Yang
Candelaria Jon J.
Holm Paige M.
Koch William F.
Motorola Inc.
Tsai H. Jey
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