Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-05-06
2001-01-30
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S528000
Reexamination Certificate
active
06180995
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to electronic integrated circuits (ICs) and more particularly the invention relates to passive devices such as inductors and capacitors of an IC having reduced parasitic substrate capacitance.
The quality, Q, of inductors and capacitors is a strong function of the losses within such devices. Losses can be caused by parasitic series resistances or parasitic shunting capacitances for example. High quality IC inductors and capacitors are required in order to realize on-chip matching elements, narrow-band circuits, filter networks, and transformers, for example. However, typical integrated inductors and capacitors on silicon substrates have low quality factor due to the parasitic capacitance with the substrate. The typical Q for a silicon substrate is in the range of 3 to 6 . In high power RF applications, higher quality elements are required in order to minimize power losses since the parasitic capacitance will shunt to the substrate some of the RF signal.
IC inductors consist of metal spirals formed on thick oxides and high-resistivity epitaxial silicon substrates. The high dielectric constant of the layers under the spiral inductor result in significant parasitic capacitance. See
FIGS. 1A and 1B
which are a section view of a metal spiral inductor
10
formed on a thick field oxide
12
on a high resistivity epitaxial silicon layer
14
and grounded substrate
16
. As shown in the schematic of
FIG. 1B
, the inductor
10
has parasitic capacitance
18
with the epitaxial layer
14
and substrate
16
. Prior art structures for increasing the quality of inductive devices in an IC include etching the silicon substrate under the capacitive structures and thereby forming a low dielectric constant air gap between the capacitive devices and the substrate. See for example Chang et al.“Large Suspended Inductors on Silicon and Their Use in a 2&mgr;m CMOS RF Amplifier” IEEE Electron Device Letters, vol. 14 , No. 5, May 1993; Ribas et al.“Micromachined Planar Spiral Inductor in Standard GaAs HEMT MMIC Technology” IEEE Electron Device Letters, vol. 19 , No. 8 , August 1998; Paek et al. “Air-Gap Stacked spiral Inductor” IEEE Microwave and Guided Wave Letter, Vol. 7, No. 10, Oct. 1997. Other techniques used to form high quality inductors with low parasitic capacitance include the use of a thick polyimide material under the inductors. However, this requires complex processing with a back-end process which is not compatible with temperatures greater than 450° C. Additionally, very thick oxides have been used to separate the metal layers from the underlying substrate. However, when film thickness increases, stress increases resulting in cracking and peeling. Further, long deposition times are required. U.S. Pat. No. 5,742,091 to Hebert teaches the formation of deep trenches under inductors to minimize parasitic capacitance.
The present invention is directed to a process and resulting structure for a passive device having high quality and which is compatible with high temperature standard silicon processing which can be implemented at the beginning, middle, or end of an integrated circuit fabrication process.
SUMMARY OF THE INVENTION
In accordance with the invention a passive electrical component structure is fabricated on a major surface of a semiconductor body by forming a field oxide layer on the major surface, at least one patterned metal layer on the field oxide layer which forms the electrical component, and a sealed air-gap formed in the semiconductor body underlying the at least one patterned metal layer. The patterned metal layer can have a generally spiral configuration and function as an inductor, or the at last one patterned metal layer can include a first metal plate spaced from a second metal plate and function as a capacitor.
In fabricating the passive electrical device, a field silicon oxide layer is formed on a major surface of the semiconductor body with a patterned metal layer formed on the field silicon oxide, either before or after other process steps. A plurality of openings are formed through the field silicon oxide and expose the underlying major surface of the semiconductor body which is then isotropically etched to form an air-gap in a semiconductor body under the field silicon oxide. The plurality openings are then sealed with deposited silicon oxide. In a process including formation of an active device having a gate electrode on the major surface of the semiconductor substrate, the step of sealing the plurality of openings can include forming gate passivation for the active device. In one embodiment a plurality of air-gaps can be formed in the semiconductor body underlying the field oxide.
Preferably, the semiconductor body includes a silicon substrate and a high resistivity epitaxial layer with the epitaxial layer having the major surface.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
REFERENCES:
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patent: 4418470 (1983-12-01), Naster et al.
patent: 5095357 (1992-03-01), Andoh et al.
patent: 5384486 (1995-01-01), Konno et al.
patent: 5532506 (1996-07-01), Tserng
patent: 5742091 (1998-04-01), H{acute over (e)}bert
patent: 5844299 (1998-12-01), Merrill et al.
J.Y.-C.Chang, “Large Suspended Inductors on Silicon and Their Use in a 2-&mgr;m CMOS RF Amplifier,” IEEE Electreon Device Letters, vol. 14, No. 5, May 1993.
S.W. Paek and K.S. Seo, “Air-Gap Stacked Spiral Inductor,” IEEE Microwave and Guided Wave Letters, vol. 7, No. 10, Oct. 1997.
R.P. Ribas, J. Lescot, J.L. Leclercq, N. Bennouri, J.M Karam, and B. Courtois, “Micromachined Planar Spiral Inductor in Standard GaAs HEMT MMIC Technology,” IEEE Electron Device Letters, vol. 19, No. 8, Aug. 1998.
Meier Stephen D.
Spectrian Corporation
Townsend and Towsend and Crew LLP
Woodward Henry K.
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