Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2000-08-29
2003-02-04
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S679000, C324S754090, C324S757020, C324S762010
Reexamination Certificate
active
06515358
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of semiconductor testing and packaging and more particularly to integrated circuit bond pad exposure, packaging, and testing.
2. Description of Related Art
In the manufacture of semiconductor devices, it is advisable that such devices be tested at the wafer level to evaluate their functionality. The process in which die in a wafer are tested is commonly referred to as “wafer sort.” Testing and determining design flaws at the die level offers several advantages. First, it allows designers to evaluate the functionality of new devices during development. Increasing packaging costs also make wafer sorting a viable cost saver, in that reliability of each die on a wafer may be tested before incurring the higher costs of packaging. Measuring reliability also allows the performance of the production process to be evaluated and production consistency rated, such as for example by “bin switching” whereby the performance of a wafer is downgraded because that wafer's performance did not meet the expected criteria.
FIG. 1
illustrates a surface view of the top side of an integrated circuit device. Metal interconnect lines and components of integrated circuit device
11
are formed on an underlying silicon substrate. The side of the silicon substrate on which the integrated circuit is formed shall herein be referred to as the top side of the silicon substrate. As illustrated in
FIG. 1
, bond pads
13
are located along the periphery of integrated circuit device
11
. In the center of integrated circuit device
11
is the active region
12
containing the majority of the high density, active circuitry of integrated circuit device
11
. To activate the circuitry within active region
12
, it is necessary to supply voltage signals to bond pads
13
. These voltage signals are supplied to bond pads
13
through a package to which integrated circuit device
11
is affixed.
FIG. 2
illustrates a cross-section of integrated circuit device
11
after packaging. After integrated circuit device
11
is affixed to package substrate
15
, individual bond wires
14
are used to electrically couple each bond pad
13
to a corresponding pad on package substrate
15
. Each corresponding pad
13
on package substrate
15
is then individually coupled to an external pin
16
. The packaged integrated circuit device of
FIG. 2
may then be placed within a socket in order to electrically couple external pin
16
to drivers that supply the necessary voltage signal to activate integrated circuit device
11
. As illustrated in
FIG. 2
, integrated circuit device
11
is mounted to package substrate
15
with its top-side facing away from package substrate
15
. In this manner, once integrated circuit device
11
is activated through package pin
16
, the internal, active region
12
may be accessed and probed for testing since neither bond pads
13
, package substrate
15
, nor bond wires
14
obscure access to this region of integrated circuit device
11
.
FIG. 3
illustrates a top-side view of a second bond pad configuration on an integrated circuit device. As illustrated in
FIG. 3
, bond pads
21
of integrated circuit device
20
are formed along the top of the entire integrated circuit device so that the bond pads now reside directly over the active circuitry region of integrated circuit device
20
. By forming bond pads in both the center and periphery of integrated circuit device
20
, more bond pads can be placed across the surface of the device than can be placed only within the peripheral region. In addition, active circuitry which underlies bond pads
21
of integrated circuit device can be directly coupled to its nearest bond pad using relatively short interconnect lines. This minimizes the resistive, capacitive, and inductive effects associated with routing interconnect lines over long distances, improving speed performance.
FIG. 4
is an illustration of a cross-section of integrated circuit device
20
after mounting to a package substrate
22
. In order to mount integrated circuit device
20
to package substrate
22
, solder balls
24
are placed on each of bond pads
21
to electrically couple each bond pad
21
to its corresponding pad on package substrate
22
. Each corresponding pad on package substrate
22
is, in turn, coupled to an external pin
23
. Integrated circuit device
20
is mounted to package substrate
22
with its top-side facing towards the package substrate. In other words, in comparison to the method used to mount integrated circuit device
11
to its package substrate in
FIG. 2
, integrated circuit device
20
is “flipped.” For this reason, the design of integrated circuit device
20
illustrated in FIG.
3
and its subsequent packaging method illustrated in
FIG. 4
is referred to as flip-chip technology. The technology is also known as Controlled Collapsable Chip Connection (C
4
), named after the package mounting technique of using solder to replace bond wires.
Integrated circuit device
11
(as shown in
FIG. 1
) or integrated circuit device
20
(as shown in
FIG. 3
) illustrate bond pads
13
and
21
, respectively, available for electrical coupling to a corresponding pad on package substrate,
15
and
22
, respectively. In general, after the device is made, bond pads
13
and
21
, respectively, lie beneath dielectric layers and must be exposed for bonding to package
15
and
22
, respectively. In the typical process, bond pads
13
and
21
, respectively, are covered by a hard passivation layer of, for example, silicon nitride (Si
3
N
4
). This hard passivation layer is covered by a soft passivation layer of, for example, a photodefinable polyimide. The hard and soft passivation layers protect the device from the ambient, for example, scratches, moisture, and impurities.
FIGS. 5-8
illustrate the prior art process for exposing bond pads
13
or
21
, respectively.
FIG. 5
shows an integrated circuit structure
50
with bond pad
55
overlying structure
50
. Examples of conventional bond pads include aluminum (Al), aluminum-copper (Al—Cu) alloy, aluminum-copper-silicon (Al—Cu—Si) alloy metal bond pads. Overlying bond pad
55
is hard passivation layer
60
, such as for example, Si
3
N
4
. Above Si
3
N
4
layer
60
is a soft passivation layer
65
, such as for example, a photodefinable polyimide passivation layer.
FIG. 5
illustrates the first processing step of exposing bond pad
55
to a light source. In this step, a portion
70
of photodefinable polyimide layer
65
is protected from light exposure. The remaining photodefinable polyimide layer
65
is exposed to ultraviolet light and developed. During development, the unexposed region of photodefinable polyimide layer
65
is dissolved, exposing Si
3
N
4
hard passivation layer
60
in that area.
FIG. 6
shows the second step in the prior art process of exposing the integrated circuit bond pad. In
FIG. 6
, the exposed Si
3
N
4
layer
65
is etched to remove Si
3
N
4
from an area above bond pad
55
. A suitable etchant is, for example, a NF
3
/He and SF
6
/He etch chemistries.
Once bond pad
55
is exposed, the wafer is cured through a pad cure step as shown in FIG.
7
. The pad cure step cures the remaining photodefinable polyimide layer
65
. The curing step also results in degassing/outgassing of particles from polyimide layer
65
, in part, particles resulting from the prior Si
3
N
4
etching step, to form on bond pad
55
. Further, the curing step is a high temperature cure which oxidizes a portion of bond pad
55
. Thus, for example, oxidized aluminum metal becomes alumina or sapphire which forms a hard coating on bond pad
55
.
FIG. 7
shows oxidized and particle residual layer
70
formed on bond pad
55
. In order to bond a suitable package wire to bond pad
55
or to test the integrated circuit at bond pad
55
, residual layer
70
must be diminished or removed. Thus,
FIG. 8
shows a cleaning step of a sputter etch that is typically used to remove residual layer
75
to expose bond pad
55
. Since the
Dass M. Lawrence A.
Karklin Kenneth D.
Roggel Amir
Seshan Krishna
Berezny Nema
Intel Corporation
Nguyen Tuan H.
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