Integrated parity-based testing for integrated circuits

Details Integrated parity-based testing for integrated circuits Integrated parity-based testing for integrated circuits

1990-12-20

1993-03-09

Canney, Vincent P.

Excavating

371 225, G01R 3128

Patent

active

051930927

ABSTRACT:
An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.

REFERENCES:
patent: 4749947 (1988-06-01), Gheewala
Williams, Thomas W. et al., "Design for Testability-A Survey", IEEE Transactions on Computers, vol. C-31, No. 1, Jan. 1982, pp. 2-13.
Goldstein, Lawrence H. et al., "SCOAP: Sandia Controllability/Observability Analysis Program" Sandia National Laboratories, pp., 190-196.

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