Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-09-24
2003-03-04
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S124000, C438S126000, C438S127000
Reexamination Certificate
active
06528351
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated monolithic structure containing one or more electronic systems and, in particular, to a substrate containing one or more integrated circuit chips placed in the substrate such that the top surface of each chip contains electrically conductive lands or electrically conductive pads and is substantially coplanar with the top surface of the substrate such that conductive traces can be formed over the top surfaces of the integrated circuit chips and the substrate to interconnect integrated circuit chips into one or more desired electronic systems.
BACKGROUND OF THE INVENTION
For many years, the semiconductor industry has been attempting to fabricate a system on a chip. In particular, the industry has attempted to combine linear and digital circuitry on the same chip and often to include memory on the chip to provide an electronic system on a single integrated circuit chip. Unfortunately, the additional processing steps create yield loss such that if a single component of the chip fails, all components on the chip are useless. As a result, multi-chip modules in particular are commonly used to create electronic systems.
Some companies have combined logic and memory on a chip. Microprocessors, programmable logic and graphics circuits, in particular, incorporate logic circuitry together with memory.
Accordingly, there exists a need for a monolithic, integrated structure which can incorporate the functions represented by semiconductor chips fabricated using different technologies, such as analog and digital, so as to form one or more partial or entire electronic systems.
SUMMARY OF THE INVENTION
In accordance with this invention, one or more integrated circuit chips is placed or are combined in a substrate such that the chip or chips can be electrically contacted or interconnected using standard photolithographic processes to form a single integrated circuit package or an electronic system. The chips can be from different technologies, even from substrates that are totally incompatible. Thus, chips fabricated using silicon and gallium-arsenide technology can be placed in the monolithic structure of this invention and interconnected so as to operate together as part of an electronic system.
In addition, integrated circuit chips fabricated using normal
100
silicon can be combined using the methods of this invention with integrated circuit chips fabricated using
111
silicon as well as with gallium-arsenide chips, for example, to yield a composite structure.
The process of this invention allows semiconductor chips using different technologies to be combined in a single monolithic, integrated structure of high reliability and to be interconnected using standard photolithographic processing currently available in the semiconductor industry and/or the printed circuit board industry.
In accordance with a process of this invention, two or more integrated circuit chips of the same type or disparate types are placed in two or more cavities, respectively, in a substrate. Adhesive bonding material is placed on the surface of the cavity and in the interconnect spaces between the integrated circuit chips and the cavity walls and allowed to set thereby to adherently hold the integrated circuit chips in their respective cavities. The chips are placed in the cavities such that conductive pads face outward from the cavity and are visible as well as being substantially in the same plane as the top surface of the substrate. A conductive layer is then deposited over the top surface of the substrate and the exposed surfaces and conductive pads of the integrated circuit chips contained in the substrate cavities. Standard photolithographic techniques are then used to mask and etch the conductive layer to form a conductive interconnect pattern to interconnect the two or more chips into the desired electronic system.
In accordance with one embodiment of this invention, the integrated circuit chips can be of different types, different materials and carry out different functions, and yet when interconnected together, form a unitary monolithic electronic system of high quality and great reliability.
In accordance with another embodiment of this invention, a plastic substrate is made with cavities having sides with fixed angles such that cross-sections of the cavities are trapezoidal. The substrate may be manufactured using a mold that is custom created for each type package system. Typically, each package contains a single device or a multichip module and is substantially smaller than a standard 18 inch by 24 inch plastic substrate. Therefore, the routing pattern for each package is stepped and repeated across the plastic substrate to create a plurality of identical packages.
A plastic such as Mylar, Melinex or Delrin may be injected into the mold to produce the substrate with the desired cavities with the specific angled sidewalls, which may vary from vertical to plus or minus 45 degrees or greater. Other thermoplastic, thermoset or composite plastics could be used. All cavities are through-hole cavities and have their largest dimensions on the same side of the substrate. The thickness of the substrate can vary from a few thousandths of an inch to more than one quarter of an inch. Typically, the cavities are similar in thickness to the integrated circuits that are to be inserted into them. However, if the cavities are made using angled sidewalls, components with similar angled sides will naturally center themselves when inserted.
A planarizing layer, such as a planar stainless steel or quartz plate, of the same dimensions as the substrate, is temporarily attached to the side of the substrate where the cavity dimensions are smaller. The planarizing layer may be coated with a soft, non-sticking film, such as but not limited to Teflon. Various methods can be used to attach the substrate to the planarizing layer including clamps or temporary adhesives.
Integrated circuits and other active or passive devices that have their bonding pads on the topside in either an array or peripheral pattern are manufactured with angled sidewalls that typically match the angles of the cavities into which they will be inserted. The topsides of the integrated circuits are made to match the smaller dimensions of the substrate cavities. The angles on the sidewalls of the integrated circuits in one embodiment are made using a diamond saw whose blade has a specific angle which may match the angle created in the cavity. Alternatively, anisotropic etching can also be used to create specific angles of the sidewalls on the integrated circuits that match angles of the sidewalls of the cavities in the substrate.
The integrated circuits are inserted into their matching cavities on the substrate with their topsides on the matching bottom of the cavity and their backsides exposed. A prepreg layer (resin implanted with glass or aramid fiber) is applied to the backside of the integrated structure (i.e. to the exposed backsides of the integrated circuits and the adjacent exposed surface of the substrate) and the temperature and pressure are increased causing the prepreg material to soften and flow around the integrated circuits and into all crevices that may exist between the integrated circuits and the substrate. The temperature is lowered, the pressure is released and the cured prepreg permanently holds each integrated circuit in its respective cavity, the top side of each integrated circuit being forced into coplanarity with the top surface of the substrate. The planarizing layer may then be removed to expose the top sides with conductive pads of the integrated circuits and the coplanar top surface of the substrate.
Metal, such as copper, is deposited over the entire top surface of the structure, covering the original substrate as well as the topsides and the bonding pads of the integrated circuits. The metal may be plated or applied by other processes such as sputtering or evaporation. A photosensitive material is then applied to the metal layer and the interconnect pattern is defined
Nathan Richard J.
Shepherd William H.
JigSaw tek, Inc.
Picardat Kevin M.
Silicon Valley Patent & Group LLP
Suryadevara Onkar
LandOfFree
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