Integrated P+ implant sequence in DPDM process for suppression o

Details Integrated P+ implant sequence in DPDM process for suppression o Integrated P+ implant sequence in DPDM process for suppression o

1995-03-17

1995-10-24

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 34, 437 44, H01L 218238

Patent

active

054609984

ABSTRACT:
A new method of integrating different width spacers into a multiple polysilicon process in the fabrication of an integrated circuit is described. A semiconductor substrate is provided wherein NMOS and PMOS regions are separated by an isolation region. Gate electrodes are formed in the NMOS and PMOS regions. Lightly doped NMOS and PMOS regions are implanted into the semiconductor substrate. A dielectric layer is deposited over the gate electrodes in the NMOS and PMOS regions and etched away to leave sidewall spacers on the gate electrodes. The PMOS region is covered with a mask. Heavily doped NMOS source and drain regions are implanted into the semiconductor substrate, then the photoresist mask is removed. Thereafter, an interpoly oxide layer is deposited overlying the gate electrodes in the NMOS and PMOS regions. A contact opening is formed through the interpoly oxide layer to the gate electrodes within the NMOS region. A layer of polysilicon is deposited overlying the interpoly oxide layer and within the contact opening and patterned wherein the polysilicon layer within the PMOS region is removed. The NMOS region is covered with a photoresist mask. The interpoly oxide layer not covered by the mask is etched away to leave a second set of spacers on the sidewalls of the gate electrodes within the PMOS region. Heavily doped PMOS source and drain regions are implanted into the semiconductor substrate and the photoresist mask is removed. The fabrication of the integrated circuit may now be completed.

REFERENCES:
patent: 4760033 (1988-07-01), Mueller
patent: 5091763 (1992-02-01), Sanchez
patent: 5183771 (1993-02-01), Mitsui et al.
patent: 5405791 (1995-04-01), Ahmad et al.
"Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFET 's Using a Quasi-Two-Dimensional Analytical Model", by Parke et al., IEEE Transactions on Electron Devices, vol. 39, No. 7, Jul. 1992, pp. 1694-1702.

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