Integrated output buffer logic circuit with a memory circuit

Details Integrated output buffer logic circuit with a memory circuit Integrated output buffer logic circuit with a memory circuit

1991-02-13

1992-02-11

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 3072471, 307480, H03K 190175, H03K 1900

Patent

active

050878409

ABSTRACT:
An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

REFERENCES:
patent: 3924193 (1975-12-01), Wolff
patent: 3942042 (1976-03-01), Nikami
patent: 3947697 (1976-03-01), Archer et al.
patent: 4480198 (1984-10-01), Gass
patent: 4525635 (1985-06-01), Gillberg
patent: 4527277 (1985-07-01), Kosaka et al.
patent: 4568881 (1986-02-01), Kostrov
patent: 4692635 (1987-09-01), Rapp
patent: 4926451 (1990-05-01), Yoshihara et al.

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