Dynamic magnetic information storage or retrieval – Head – Magnetoresistive reproducing head
Reexamination Certificate
2000-10-05
2003-12-23
Nguyen, Hoa T. (Department: 2652)
Dynamic magnetic information storage or retrieval
Head
Magnetoresistive reproducing head
Reexamination Certificate
active
06667860
ABSTRACT:
BACKGROUND
The following invention relates to the protection of magnetoresistive (“MR”) sensor from electrostatic discharge (“ESD”) or electrical overstress (“EOS”). Electrostatic charge may accumulate as a result of friction or movement. An ESD event can occur when an object carrying such an accumulation of electrostatic charge contacts an electrically-grounded surface. An ESD event is a transfer of electrostatic charge from an object of greater voltage to an object of lesser voltage. An ESD event often yields a momentary electrical current of significant voltage that is capable of disabling the delicate circuits contained on the MR sensor. Electrostatic discharge events are very common and can be highly destructive to MR sensors. EOS occurs when a MR sensor is subjected to voltages or currents beyond those intended for the MR sensor's operation, typically during events considerably longer in duration than ESD events. An example of EOS is the electrical testing of MR sensors at inappropriate voltages. Similar to ESD, EOS is capable of damaging the MR sensors. Those practiced in the art often refer to “ESD” when referring either to electrostatic discharge or to electrical overstress. The term “ESD” will be used in this patent to refer to both.
The ESD damage to a MR sensor may render the entire device inoperable, in which case protection from ESD is a highly desirable goal. For example, the failure of a MR sensor in a recording head of a hard drive may incapacitate the recording head and cause the hard drive to fail.
MR sensors in modem recording heads are susceptible to stray electric charges, fields, and currents. To provide increased areal storage densities, head feature sizes are decreasing, which can exacerbate this problem. Existing MR sensors already display sensitivity to ESD events as small as 1V in magnitude, with that sensitivity slated to steadily increase in the future. Protection from ESD events in MR sensors throughout production, drive assembly, and customer use is therefore a large and growing concern.
Prior art systems exist for protection of integrated circuits from ESD events. For example, conventional diodes may be wired in parallel to a resistive element to offer a shunt for ESD power. These diodes may be configured back-to-back, depending on the level of protection desired, as on-wafer protection in the semiconductor industry. Similar efforts could be made in the MR industry to offer protection to dielectric gaps or to the reader stripe, but the difficulty in processing semiconductors on a MR wafer might render such solutions cost prohibitive.
Prior art systems have several disadvantages. Generally, the prior art systems can be inconvenient, large, late-stage, weak, or single-use. Simply put, the objective of using ESD protection is to lengthen the usable life span of an IC-based component. An ESD protection method that is either too large or inconvenient for the situation will not likely be used. If an ESD protection is late-stage, it may not be implemented in time to protect an IC from ESD events during manufacture and assembly. Also, ESD protection that is weak may not be effective against strong ESD events. Single-use ESD protection only protects the IC for one ESD event. Once it is used, no further protection is offered.
Accordingly, it is desirable to provide ESD protection that is convenient, sized appropriately, implemented at an early stage of manufacture, strong, and yet reusable.
SUMMARY OF THE INVENTION
The present invention is directed to a device and a method for the protection of a magnetoresistive (“MR”) sensor from electrostatic discharge or electrical overstress
The circuit includes a magnetoresistive sensor and a tunnel junction device coupled to the MR sensor to dissipate the energy associated with an electrical signal exceeding operational voltages for the sensor. The tunnel junction can include a first conducting layer, a second conducting layer, and a barrier material positioned between the first and the second conducting layer. The barrier material can be positioned so that the first conducting layer and the second conducting layer do not make contact.
The MR sensor can be connected in parallel to the first and second conducting layer. The tunnel junction can be made of a material with a resistance more than the MR sensor's resistance at operational voltages and a resistance below the MR sensor's resistance at larger voltages.
The protected circuit can include a magnetoresistive sensor with resistance of approximately 70&OHgr;. The operational voltage range of the sensor can include a range of approximately 0.2V±0.1V, operating at up to approximately 1 GHz. The tunnel junction further comprises a capacitance of approximately 1 pF and a resistance of greater than 1 k&OHgr; at the operational voltages of the MR sensor and 1&OHgr; at the higher voltages.
The first conducting layer can include a first metal layer, the second conducting layer can include a second metal layer, and the barrier material can include an insulating material. The barrier material can include an area of approximately 30 &mgr;m
2
a thickness of approximately 35 Å, an energetic barrier for electrons of approximately 0.35 eV between its conduction band and Fermi level, and a capacitance of approximately 1 pF. The barrier material can include a thin film barrier material.
The tunnel junction further can include an insulating barrier made of one or more materials, such as SiN
x
, SiO
x
, CaF
2
, Al
2
O
3
, and AlN. The junction can include an insulating barrier material made of one or more semiconductive materials, such as Si, amorphous Si, poly-Si, Ge, SiGe, GaAs, GaAlAs, ZnSe, ZnS, CdSe, and CdS.
The tunnel junction can exhibit a process, such as tunneling of electrons, thermionic emission, and thermionic field emission, to achieve a super-linear dependence of current on voltage during the change of state of the tunnel junction when the MR sensor is at the conventional voltages and when the MR sensor is at the larger voltages. The tunnel junction can be coupled to the MR sensor during fabrication of the circuit.
In another aspect of the invention, a method for fabricating the protected circuit including integrating a MR sensor on the circuit and coupling a tunnel junction to the MR sensor to dissipate an electrical signal exceeding operational voltages for the MR sensor is presented. The tunnel junction device can be fabricated during the fabrication of the circuit. The method can include fabricating the tunnel junction on the MR sensor.
The invention accordingly includes the features of construction, combination of elements and arrangement of parts that will be exemplified in the following detailed disclosure, and the scope of the invention will be indicated in the claims. Other features and advantages of the invention will be apparent from the description, the drawings, and the claims. This invention can include one or more of the following advantages:
The ESD protection device can be capable of withstanding multiple, high-voltage ESD events throughout the lifecycle of the integrated circuit. The shunting of current through the ESD protection device can leave both the ESD protection device and the MR sensor undamaged, meaning repeated exposures to ESD level voltages can be tolerated, with the subsequent product repeatedly returning to completely operational conditions. The energy levels a MR sensor can withstand with the ESD protection device can be greater than twenty times its unprotected levels.
The ESD protection device can be fabricated with the MR sensor during wafer-level processing. This can ensure that the MR sensor is protected during fabrication of the integrated circuit, through packaging, and throughout the lifecycle of the integrated circuit.
The ESD protection device disclosed may not require highly-pure, highly-crystalline semiconductor materials.
REFERENCES:
patent: 5019530 (1991-05-01), Kleinsasser et al.
patent: 5142263 (1992-08-01), Childers et al.
patent: 5614727 (1997-03-01), Mauri et al.
patent: 5677867 (19
Granstrom Eric Leroy
Tabat Ned
Chen Tianjie
Nguyen Hoa T.
Seagate Technology LLC
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