Integrated multiport switch having independently resettable mana

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

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H04J 302

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active

059913053

ABSTRACT:
An integrated multiport switch (IMS) in which an on-chip management information base (MIB) accumulation processor enables monitoring of a significantly larger number of MIB objects to be stored in external memory while minimizing media access controller (MAC) complexity. A MAC for each port in the IMS outputs a MIB report for each transmission or reception of data according to a specific compressed format to a MIB engine that can be centrally located on the chip. The MIB engine decodes the MIB report into a plurality of associated MIB objects, which are temporarily accumulated until the external memory is updated. The MIB engine initiates the stored MIB value updating process by retrieving the values from the external memory and adding the accumulated MIB objects to the retrieved values. The updated MIB objects are then transmitted back to the external memory for storage therein and the MIB engine object values are cleared. Reset of the MIB related storage elements in response to an external data signal is effected independently of other chip logic elements.

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Wright, M.: "Network-switch ICs simplify design and slash per-port costs", EDN Electrical Design News, vol. 40, No. 24, Nov. 23, 1995, pp. 53-56, 58, 60, XP000546015.
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