Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-08-15
2009-08-11
Dharia, Prabodh M. (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S094000, C345S098000, C345S100000, C345S103000
Reexamination Certificate
active
07573452
ABSTRACT:
Integrated multiplexer/de-multiplexer for a pixel array is provided. A drive circuit having the de-multiplexer is provided to a gate line arranged for a pixel array. A pixel is selected using the drive circuit. A read circuit having the multiplexer is provided to a data line arranged for the pixel array. Data output from a pixel is read using the read circuit.
REFERENCES:
patent: 4758831 (1988-07-01), Kasahara et al.
patent: 4963860 (1990-10-01), Stewart
patent: 4975691 (1990-12-01), Lee
patent: 5051739 (1991-09-01), Hayashida et al.
patent: 5222082 (1993-06-01), Plus
patent: 5686935 (1997-11-01), Weisbrod
patent: 5712653 (1998-01-01), Katoh et al.
patent: 5784042 (1998-07-01), Ono et al.
patent: 5790234 (1998-08-01), Matsuyama
patent: 5870071 (1999-02-01), Kawahata
patent: 6232939 (2001-05-01), Saito et al.
patent: 6300928 (2001-10-01), Kim
patent: 6345085 (2002-02-01), Yeo et al.
patent: 6597203 (2003-07-01), Forbes
patent: 6661397 (2003-12-01), Mikami et al.
patent: 6873320 (2005-03-01), Nakamura
patent: 2001/0020926 (2001-09-01), Kuijk
patent: 2001/0026121 (2001-10-01), Khan et al.
patent: 2001/0026179 (2001-10-01), Saeki
patent: 2001/0052898 (2001-12-01), Osame et al.
patent: 2002/0011981 (2002-01-01), Kuijk
patent: 2002/0015031 (2002-02-01), Fujita et al.
patent: 2002/0015032 (2002-02-01), Koyama et al.
patent: 2002/0030528 (2002-03-01), Matsumoto et al.
patent: 2002/0080108 (2002-06-01), Wang
patent: 2002/0101433 (2002-08-01), McKnight
patent: 2002/0130686 (2002-09-01), Forbes
patent: 2002/0154084 (2002-10-01), Tanaka et al.
patent: 2002/0190971 (2002-12-01), Nakamura et al.
patent: WO 94/25954 (1994-11-01), None
Karim Karim S.
Kumar Anil
Mohan Nitin
Nathan Arokia
Sakariya Kapil
Dharia Prabodh M.
Ignis Innovation Inc.
Pearne & Gordon LLP
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