Integrated multichip memory module structure

Details Integrated multichip memory module structure Integrated multichip memory module structure

1993-09-13

1996-03-26

Nelms, David C.

Static information storage and retrieval

Format or disposition of elements

365 63, 257686, 257724, 361735, 361728, G11C 502

Patent

active

055026672

ABSTRACT:
An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

REFERENCES:
patent: 2907926 (1959-10-01), Slack
patent: 3029495 (1962-04-01), Doctor
patent: 3065384 (1962-11-01), Sprude
patent: 3070729 (1962-12-01), Heidler
patent: 3139559 (1964-06-01), Heidler
patent: 3152288 (1964-10-01), Mittler
patent: 3370203 (1968-02-01), Kravitz et al.
patent: 3746934 (1973-07-01), Stein
patent: 3748479 (1973-07-01), Lehovec
patent: 4520427 (1985-05-01), Brotherton et al.
patent: 4525921 (1985-07-01), Carson et al.
patent: 4551629 (1985-11-01), Carson et al.
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4638348 (1987-01-01), Brown et al.
patent: 4646128 (1987-02-01), Carson
patent: 4706166 (1987-11-01), Go
patent: 4727410 (1988-02-01), Higgins, III
patent: 4764846 (1988-08-01), Go
patent: 4801992 (1989-01-01), Golubic
patent: 4818728 (1989-04-01), Rai et al.
patent: 4833568 (1989-05-01), Berhold
patent: 4862249 (1989-08-01), Carlson
patent: 4868712 (1989-09-01), Woodman
patent: 4879258 (1989-11-01), Fisher
patent: 4894706 (1990-01-01), Sato et al.
patent: 4901136 (1990-02-01), Neugebauer et al.
patent: 4902641 (1990-02-01), Koury, Jr.
patent: 4926241 (1990-05-01), Carey
patent: 4956746 (1990-09-01), Gates, Jr. et al.
patent: 4983533 (1991-01-01), Go
patent: 5016138 (1991-05-01), Woodman
patent: 5019943 (1991-05-01), Fassbender et al.
patent: 5019946 (1991-05-01), Eichelberger et al.
patent: 5051865 (1991-09-01), Kato
patent: 5064771 (1991-11-01), Solomon
patent: 5071792 (1991-12-01), VanVanno et al.
patent: 5091331 (1992-02-01), Delgado et al.
patent: 5162254 (1992-11-01), Usui et al.
patent: 5266833 (1993-11-01), Capps
patent: 5347428 (1994-09-01), Carson et al.
Future Generations Computer Systems, vol. 4, No. 2, Sep. 1988, Amsterdam NL --Kurokawa et al. "3-D VLSI Technology in Japan and an Example: a Syndrome Decoder for Double Error Correction".
Stolle, "Edge-Mounted Chip Assembly For Microprocessor", IBM Technical Disclosure Bulletin, vol. 23, No. 2, pp. 581-582, Jul. 1980.
Carson, "Unconventional focal-plane architecture (FPA)", SPIE, vol. 225, IR Image Sensor Tech., pp.34-37, 1980.
Parks, "Batch-Fabricated Three-Dimensional Planar Coaxial Interconnections or Microelectronic Systems," IEEE Trans. on Computers, vol. C-20, No. 5, pp. 504-511, May 1971.
Agusta et al., "High Density Packaging of Monolithic Circuits", IBM Technical Disclosure Bulletin, vol. 10, No. 7, p. 890, Dec. 1967.
Bertin et al., "Evaluation of a 3D Memory Cube System", IEEE, pp. 12-15, 1993.

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