Integrated multi-layer test pads and methods therefor

Details Integrated multi-layer test pads and methods therefor Integrated multi-layer test pads and methods therefor

1999-02-23

1999-11-09

Chaudhuri, Olik

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438 6, 438 17, 438 18, 438123, 438612, 438614, H01L 2144

Patent

active

059813024

ABSTRACT:
A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.

REFERENCES:
patent: 5383093 (1995-01-01), Nagasaka
patent: 5554940 (1996-09-01), Hubacher
patent: 5623166 (1997-04-01), Olowolafe et al.
patent: 5686759 (1997-11-01), Hyde et al.
patent: 5726458 (1998-03-01), Bui
patent: 5734187 (1998-03-01), Bohr et al.
patent: 5760429 (1998-06-01), Yano et al.
patent: 5760477 (1998-06-01), Cronin
patent: 5917197 (1999-06-01), Alswede et al.

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