Integrated mosfet device with low resistance peripheral diffusio

Details Integrated mosfet device with low resistance peripheral diffusio Integrated mosfet device with low resistance peripheral diffusio

1994-10-07

1996-08-13

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257754, 257773, 257774, 257382, 257751, 257296, H01L 2348, H01L 2352, H01L 2940

Patent

active

055459269

ABSTRACT:
A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

REFERENCES:
patent: 4322736 (1982-03-01), Sasaki et al.
patent: 4874719 (1989-10-01), Kohyama et al.
patent: 5237187 (1993-08-01), Suwanai et al.
patent: 5294822 (1994-03-01), Verrett
1987 Symposium on VLSL Technology, Digest of Technical Papers, p. 93 (A High Density 4Mbit dRAM Process Using a Fully Overlapping Bitline Contact (FOBIC) Trench Cell, K. H. Kusters, et al. (1987).

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