Integrated memory with two burst operation types

Details Integrated memory with two burst operation types Integrated memory with two burst operation types

2000-09-14

2001-10-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S236000, C365S240000, C365S230040

Reexamination Certificate

active

06310824

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having two different burst operating modes.
Integrated memories usually have memory cells which are arranged in rows and columns. The rows can be accessed by means of row addresses and the columns can be accessed by means of column addresses. In some synchronous integrated memories, such as, for example, DDR SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories), when an external column address is applied in accordance with predetermined specifications, an access is made to a plurality of columns whose addresses succeed one another in a specific manner. Such an access is referred to as a “burst access”.
The invention is based on the object of specifying an integrated memory having two different burst operating modes in which, for each burst operating mode, a different addressing order of the columns takes place during a burst access and which can be realized using relatively few components.
This object is achieved by means of an integrated memory in accordance with claim
1
. The dependent claims relate to advantageous designs and developments of the invention.
In the memory according to the invention, a plurality of internal column addresses are generated from an external column address, fed to said memory, during each burst access. The order of these internal column addresses is dependent on the respective burst operating mode in which the memory is situated. The internal column addresses are composed of part of the external column address and a partial address generated by the bidirectional address counting unit. During each counting step of the address counting unit, another partial address and thus also another internal column address are generated. The address counting unit has the second counting direction whenever the memory is situated in the second burst operating mode or whenever it is situated in the first burst mode while, at the same time, the second least significant address bit of the external column address has a second logic state. By contrast, the address counting unit has the first counting direction when the memory is situated in the first burst operating mode and when, at the same time, the second least significant address bit of the external column address has the first logic state. In the second burst operating mode, the transformation unit serves for transforming the partial address fed to the second column decoder, provided that the least significant address bit of the external column address has a first logic state. In the other cases, that is to say when the least significant address bit has a second logic state or when the memory is situated in the first burst operating mode, the transformation unit directs the partial addresses generated by the address counting unit without transformation, that is to say unchanged, to the second column decoder. The transformation, which is performed by the transformation unit in the case mentioned, consists in the partial addresses fed to the transformation unit being incremented by the latter in each case by a specific value.
According to a first embodiment of the invention, the address counting unit is a bidirectional counter and the transformation unit is a unidirectional counter. According to a second embodiment, the address counting unit has a bidirectional shift register and the transformation unit has a unidirectional shift register.
The invention is explained in more detail below with reference to the figures, in which:


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