Static information storage and retrieval – Powering
Reexamination Certificate
2001-11-13
2003-04-08
Tran, M. (Department: 2818)
Static information storage and retrieval
Powering
C365S230060
Reexamination Certificate
active
06545930
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated memory having a memory cell array with row lines for selecting memory cells and column lines for reading out or writing data signals to/from the memory cells. The memory further has a voltage regulating circuit with a terminal for a regulatable supply voltage for application to one of the row lines.
An integrated memory generally has a memory cell array containing column lines and row lines. In this case, the memory cells are disposed at crossover points of the column lines and the row lines. The memory cells are each connected to one of the row lines. For the purpose of selection, by way of example, selection transistors of memory cells are turned on by an activated row line, as a result of which a data signal of a corresponding selected memory cell can subsequently be read out or written. To that end, the selected memory cell is connected via the selection transistor to one of the column lines, via which the corresponding data signal is read out or written in, respectively.
In an inactive state, the row lines are deactivated and, to that end, are precharged to a precharge potential for example. To that end, the respective row lines are applied to a corresponding supply voltage. In this case, it is advantageous in particular in memory cell arrays having comparatively small structural widths to generate the supply voltage from a so-called back-bias voltage of the cell array (voltage present across the substrate or across the well of the cell array) in such a way that this has a negative value relative to a reference-ground voltage of the memory without the back-bias voltage being altered. As a result, in particular, leakage currents of the selection transistors are effectively reduced even in the case of comparatively small structural widths.
In order to generate such a precharge voltage or supply voltage, a plurality of voltage regulating circuits are usually used for a respective memory bank, which generate from the back-bias voltage the respective required supply voltage which is applied to the row lines in the deactivated state. In order to be able to alter the target value for the precharge voltage at later times after the fabrication of the memory chip, the corresponding voltage regulating circuits are configured such that they are trimmable for the purpose of generating the precharge voltages. By feeding trimming signals to the respective voltage regulating circuit, it is possible for the corresponding precharge voltages to be adapted, for example on account of process fluctuations, to them and to be set accordingly. The trimmability requires the feeding of digital trimming signals for each voltage regulating circuit.
Since, in addition to address lines, generally a multiplicity of further lines are routed at the edge of a memory bank in the vicinity of the row decoder, in the region of which the precharge voltage is applied to the row lines for the purpose of deactivating the row lines, the provision of additional lines for trimming signals is associated with an additional space requirement on the memory chip.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory having a voltage regulating circuit that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the trimming of the voltage regulating circuit is made possible in conjunction with a comparatively small area requirement.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The memory contains a memory cell array having memory cells, row lines for selecting the memory cells, and column lines for reading out or writing data signals to/from the memory cells. A row decoder is connected to the memory cell array for activating the row lines. Address lines are connected to the row decoder, the address lines transferring address signals. A voltage regulating circuit is connected to the memory cell array and has a terminal for a regulatable supply voltage for application to one of the row lines. A driving circuit is provided for setting the regulatable supply voltage, and the driving circuit is connected to the address lines and to the voltage regulating circuit.
The transfer of trimming signals for the voltage regulating circuit via address lines that are connected to the row decoder enables the trimming of the voltage regulating circuit in conjunction with a comparatively small area requirement. During normal operation of the memory, the address lines serve for selecting row lines to be activated. The driving circuit is connected to the address lines for the purpose of setting the supply voltage. Since generally a relatively large number of address lines are disposed in the region of the row decoder, the address lines can be utilized for transferring signals to the driving circuit. Since the precharge voltage or supply voltage for deactivating the row lines is usually applied to the respective row lines in the region of the row decoders, the line routing of the address lines need not, moreover, be modified.
The trimming of the voltage regulating circuit is carried out for example during or after the initialization of the memory. To that end, the memory advantageously has programmable elements for instance in the form of programmable fuses which enable non-volatile storage of trimming signals. In order to carry out the trimming, the programmable elements are connected to the address lines by which the trimming signals are distributed over the memory chip and are transferred into corresponding driving circuits.
In an advantageous refinement of the invention, the memory has storage circuits that are connected between the address lines and the driving circuit. These serve for storing trimming signals that are transferred on the address lines. By the storage circuits, it is possible to carry out a so-called soft set for the driving circuit. The storage circuits contain, for example, bistable multivibrators that are set by the address lines.
In order to control the transfer of trimming signals between the storage circuits and the address lines, the memory preferably has a control line connected to the storage circuits. The control line enables the setting of the storage circuits by the address lines. The transfer of trimming signals via the address lines and also the subsequent storage of the trimming signals in storage circuits for transferring the signals into the driving circuit make it possible to limit the number of lines required for trimming to a single line in the region of the row decoder. This enables a comparatively small additional area requirement for line routing in the vicinity of the row decoder.
In a further advantageous development of the memory, the memory cell array is subdivided into individual series segments that are each isolated from one another by sense amplifiers. In this case, the series segments are disposed next to one another in the direction of the address lines. A plurality of the series segments are respectively assigned one of a plurality of driving circuits and one of a plurality of voltage regulating circuits. This results in a largely constant system that is insensitive to voltage drops. In particular, indirect influencing by the supply voltage applied to the deactivated row lines by instances of coupling-in is avoided. Since the individual series segments are disposed next to one another in the direction of the address lines, these can advantageously be used for transferring trimming signals without necessitating additional lines or a change to the line routing.
If the respective voltage regulating circuits of these series segments are additionally connected to a common line for the supply voltage, then voltage increases on account of comparatively high currents are avoided to a more extensive degree. The current loading along the common line is rendered uniform by a plurality of connected voltage regulating circuits.
In accordance
Fischer Helmut
Schnabel Joachim
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Tran M.
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