Integrated memory controller

Details Integrated memory controller Integrated memory controller

2007-10-23

2007-10-23

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000

Reexamination Certificate

active

11542862

ABSTRACT:
A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.

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