Integrated memory controller

Details Integrated memory controller Integrated memory controller

2006-10-10

2006-10-10

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

07120084

ABSTRACT:
A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.

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