Integrated memory circuit having an improved logic row selection

Details Integrated memory circuit having an improved logic row selection Integrated memory circuit having an improved logic row selection

1986-02-04

1988-02-02

Popek, Joseph A.

Static information storage and retrieval

Addressing

365189, G11C 1140

Patent

active

047232293

ABSTRACT:
The invention relates to a (static) memory which is divided into a number of memory blocks, memory cells being arranged in rows and columns in each memory block. A row in a memory block is activated via a selection gate whereto there are applied an inverted row selection signal (which is applied to all memory blocks) and a non-inverted and an inverted block selection signal (which is applied to all section gates in a memory block). The selection gate comprises a P-MOS transistor and two parallel-connected N-MOS transistors. The junction between the P-MOS and the N-MOS transistors constitutes the gate output (for activating a row of cells). The row selection signal is applied to the gate electrode of the PMOS transistor and of a first N-MOS transistor. The inverted block selection signal is applied to the gate electrode of the other N-MOS transistor and the block selection signal is applied to the main electrode of the P-MOS transistor.

REFERENCES:
patent: 3898632 (1975-08-01), Spencer, Jr.
patent: 4542486 (1985-09-01), Anami et al.
patent: 4554646 (1985-11-01), Yoshimoto et al.

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