Integrated memory circuit having a block selection circuit

Details Integrated memory circuit having a block selection circuit Integrated memory circuit having a block selection circuit

1987-07-24

1989-07-18

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 36523006, G11C 800, G11C 502

Patent

active

048499439

ABSTRACT:
Memory cells in an integrated memory circuit are arranged in blocks and selected by block selection gates. This method of activation offers the advantage that the memory cells are accessed faster and that the power consumption is lower than in a memory which is not subdivided into blocks, because only a small group of memory cells is activated per selection operation. A block selection circuit is provided in which selection gates of two neighboring rows of memory cells have one common transistor. As a result of the multiple use of contact areas and the use of a mirror-symmetrical architecture, the lay-out can make optimum use of the available substrate surface area.

REFERENCES:
patent: 4723229 (1988-02-01), Hartgring et al.
patent: 4729118 (1988-03-01), Gelsomini

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