Static information storage and retrieval – Addressing – Multiplexing
Reexamination Certificate
2001-07-27
2003-03-25
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Multiplexing
C365S205000, C365S189020
Reexamination Certificate
active
06538950
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated memory with memory cells configured in crossing points of word lines and bit lines and relates to an integrated memory with a differential go read amplifier.
An integrated memory in the form of a DRAM (Dynamic Random Access Memory) is disclosed in Betty Prince: “Semiconductor Memories”, John Wiley & Sons, West Sussex, 2
nd
edition 1996, chapter 5.8.5 and FIG. 5.14. A pair of bit lines is connected with a differential read amplifier. This is a typical configuration for DRAMs. It is also known from the same book, FIG. 6.54 (
e
) to configure the memory cells of a DRAM, in the crossing points of a word line, with both bit lines of a bit line pair, which is connected to the same read amplifier.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory that has a space-saving construction and whereby data to be read out are amplified by a differential read amplifier.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory that includes word lines and bit lines that cross the Ad word lines and thereby define crossing points. The memory also includes memory cells that are configured at the crossing points of the bit lines and the word lines. The memory includes a differential read amplifier having a differential input and a multiplexer having a control input. The multiplexer is connected to three of the bit lines. The multiplexer, dependent on the control input, electrically connects the differential input of the read amplifier to two arbitrary ones of the three of the bit lines.
Given the inventive integrated memory, the differential read amplifier is connected via a multiplexer to three of the bit lines and the multiplexer, dependent on its control, electrically connects a differential input of the read amplifier to two of the three arbitrary bit lines connected to it.
In contrast to the prior art, the read amplifier therefore is not always connected to the same bit line pair with respect to the inventive memory. Rather, three differently combined bit line pairs result, which each have a different respective combination of two of the three bit lines.
In accordance with an added feature of the invention, the integrated memory has a first type of word lines, which have memory cells at crossing points of the first and the second bit line, and a second type of world lines, which have memory cells at crossing points of the first and the third bit line, as well as a third type of word lines, which have memory cells at crossing points of the second and the third bit line.
With the foregoing and other objects in view there is provided, in accordance with the invention, an operating method that is suitable for operating this embodiment of the integrated memory. Complementary data is stored in the two memory cells that are connected to the same world line and is read out again. When a read or a write access is performed, the two bit lines connected to these two memory cells are electrically connected via the multiplexer to the differential input of the read amplifier. Given a write access or respectively, a read access, the two memory cells, which are configured at the crossing points of two of the three bit lines, are therefore selected via the corresponding word line and are connected to the corresponding bit lines. The two corresponding bit lines are connected via the multiplexer to the read amplifier, so that data is simultaneously written into both memory cells when performing a write operation and so that data is simultaneously read out from both memory cells when performing a readout operation. Given a write access, since the read amplifier operates differentially, it generates complementary signals on the two bit lines that are electrically connected to it, so that complementary signals are also written into the two memory cells allocated to the same word line. During a read access with respect to these memory cells, the data that is complementary to one another is read out again and is amplified by the read amplifier.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory and corresponding operating method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5276641 (1994-01-01), Sprogis et al.
patent: 5570316 (1996-10-01), Lysinger
patent: 6026010 (2000-02-01), Ema et al.
patent: 6052303 (2000-04-01), Chevallier et al.
patent: RE36993 (2000-12-01), Takashima et al.
Böhm Thomas
Braun Georg
Hönigschmid Heinz
Lammers Stefan
Manyoki Zoltan
Elms Richard
Greenberg Laurence A.
Mayback Gregory L.
Nguyen Tuan T.
Stemer Werner H.
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