Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-07-12
2002-08-27
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S195000
Reexamination Certificate
active
06442100
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of integrated memory technology. More specifically, the invention pertains to an integrated memory device.
U.S. Pat. No. 5,517,446 describes an integrated memory in the form of a ferroelectric memory (FRAM or FeRAM). There, the memory cells are connected to bit lines which are respectively combined to form bit line pairs. Each bit line pair is connected to a data line pair via a sense amplifier. In the event of a write access, data are transferred to one of the memory cells via the data line pair and the sense amplifier and also the bit line pair. In the event of a read access, the data transfer takes place in the opposite direction from one of the memory cells via the bit line pair to the sense amplifier, which forwards a differential signal established on the bit line pair to the data line pair after having amplified it. In order to save energy, according to U.S. Pat. No. 5,517,446, it is always the case that only those sense amplifiers are activated via which a data transfer has to take place in the event of the current write or read access. For the same reason, the bit lines are likewise precharged only in the case in which data are to be transferred via them. This is achieved by the activation of the sense amplifier and also the precharging of the bit line pair taking place in dependence on the same signal by which the respectively selected sense amplifier is connected to the associated data line pair. This signal is decoded from column addresses by a column decoder. An output signal which is decoded by the column decoder and which the latter generates in its last decoder stage thus serves both for connecting the bit lines to the data lines, for activating the sense amplifier and also for activating the precharging of the bit line pair.
H. Fujisawa describes an FRAM in “The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory” in: IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May 1997, page 655 et seq. In that FRAM a relatively large number of bit lines are in each case assigned to the same sense amplifier. These bit lines are connected to the sense amplifier via a multiplexer.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an integrated memory which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which has a plurality of bit lines per sense amplifier, in which write or read accesses to memory cells of the memory which take place via the sense amplifier and the bit lines are influenced in a simple manner.
With the above and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a plurality of memory cells and a number m>1 bit lines connected to the memory cells, switching elements connected to the bit lines and each having a control input, a sense amplifier having an input connected via the switching elements to the bit lines for transferring data from or to the memory cells;
a circuit unit for influencing write or read operations via the sense amplifier and the bit lines, the circuit unit having an activation input for placing the circuit unit into an activated state;
a column decoder having a first decoder stage and m second decoder stages;
the first decoder stage having inputs for receiving address signals and an output connected to the activation input of the circuit unit; and
the second decoder stages each having an input connected to the output of the first decoder stage, at least one further input for receiving a further address signal, and an output connected to the control input of a respective one of the switching elements.
In other words, the integrated memory according to the invention has m>1 bit lines which are connected via a respective switching element to an input of a sense amplifier, for transferring data from or to memory cells connected to the bit lines. Furthermore, the memory has a circuit unit for influencing write or read accesses to the memory cells which take place via the sense amplifier and the bit lines, which has an activation input via which it can be put into an activated state. The memory has a column decoder having a first and m second decoder stages, the first decoder stage having inputs for feeding in address signals and an output, and the second decoder stages each having an input which is connected to the output of the first decoder stage, at least one further input for feeding in a further address signal, and an output. The outputs of the second decoder stages are connected to a control input of a respective one of the switching elements. The output of the first decoder stage is connected to the activation input of the circuit unit.
In the case of the invention, a write or read access is influenced for all the bit lines—connected to the sense amplifier—by means of the circuit unit via a common signal, namely that signal which is generated at the output of the first decoder stage. Although hierarchical decoders having a plurality of decoder stages connected in series, as are also provided by the invention, are known in principle, usually only the outputs of the last decoder stage are used for influencing circuit units connected downstream. This also applies, for example, to U.S. Pat. No. 5,517,446 A mentioned in the introduction. In the case of the invention, the control inputs of the switching elements are connected to the outputs of the second decoder stages. In addition, in the case of the invention, the output signal of the first decoder stage upstream of the second decoder stages is unconventionally used for driving the circuit unit. As a consequence of this, the circuit unit is activated via the output signal of the first decoder stage whenever one of the first switching elements is turned on via the output of an arbitrary one of the second decoder stages.
In accordance with an added feature of the invention, the circuit unit is configured to activate the sense amplifier in the activated state. According to this first embodiment of the invention, the circuit unit activates the sense amplifier in the activated state. This can be done for example by connecting the sense amplifier to a supply potential.
In accordance with an additional feature of the invention, the circuit unit connects the sense amplifier to a data line in the activated state, the data line serving for transferring, to a point outside the integrated memory, data that have been read from the memory cells and amplified by the sense amplifier. In this embodiment, the circuit unit connects the sense amplifier to a data line in the activated state, the data line serving for transferring, to a point outside the memory, data that have been read from the memory cells and amplified by the sense amplifier.
In accordance with a concomitant feature of the invention, the circuit unit precharges the input of the sense amplifier to a specific potential in the activated state.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5293332 (1994-03-01), Shirai
patent: 5347486 (1994-09-01), Urai
patent: 5511031 (1996-04-01), Grover et al.
patent: 5905689 (1999-05-01), Oh
patent: 5953275 (1999-09-01), Sugibayashi et al.
patent: 5963500 (1999-10-01), Taura
patent: 6064622 (2000-05-01), Lee et al.
patent: 6262933
Böhm Thomas
Braun Georg
Hönigschmid Heinz
Manyoki Zoltan
Röhr Thomas
No associations
LandOfFree
Integrated memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2969807