Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-07-17
2001-08-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S230030, C365S230040, C365S233100
Reexamination Certificate
active
06272035
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated memory in which two items of data which are sequentially fed to the memory can be fed in different assignments in each case to one of two groups of memory cells.
Memory devices of this type include the type known as DDR-SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories), in which data are read in or out both with the rising edge and with the falling edge of an external clock signal. They contain a first group of memory cells, to which even column addresses are assigned, and a second cell group, to which odd column addresses are assigned. Depending on whether a start address fed to the memory is even or odd, the datum transferred with the rising edge of the external clock signal must be assigned to an even or odd column address, that is to say be stored either in the first or in the second cell group. A second datum received with a subsequent negative clock edge is then fed to the respective other cell group. During read-out from a DDR-SDRAM, two items of data are simultaneously read from the two cell groups. In this case, the order of these items of data upon being output from the memory again depends on whether the start address applied to the memory in the event of read-out is even or odd.
The information as to whether the start address that is present is an even or odd address is taken from the least significant bit (LSB) of the start address. A corresponding control signal for the memory is derived from this address bit.
To date, it has been customary for corresponding input circuits, serving for assigning the successively arriving data to the different cell groups, to be provided directly at the respective data connection. It has also been customary for output circuits, which output the data read simultaneously from the two cell groups in the event of a read access to the memory in the correct order, to be provided directly at the respective data connection.
The control signal derived from the least significant bit of the start address has to be fed both to the input circuit and to the output circuit. Depending on where the control signal is generated, the latter has to be driven via the entire chip in the worst-case scenario, in particular when the data connections are provided at the edge of the memory component. This results in a not inconsiderable propagation delay of the control signal, since the line lengths can be up to several millimeters. This propagation delay limits the maximum operating speed of the memory since, in the event of a write access, the data can be fed to the cell groups only after evaluation of the control signal by the input circuit provided at the data connection. This propagation delay of the control signal is less critical in the event of a read access since the data that are read out, in SDRAMs, are buffer-stored for one or more clock periods in a FIFO store (First IN, First OUT), before being output from the memory. This means that there is enough time available for the decision concerning the order in which the data read from the cell groups are to be output.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantages of the heretofore-known memory devices of this general type and, in particular, in which the write accesses can be effected more rapidly than in conventional memory devices.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
a bidirectional data connection;
two cell groups located adjacent to one another and having memory cells;
a first local data line and a second local data line for a respective bidirectional data transfer from and to the memory cells of a respective one of the two cell groups;
a first global data line and a second global data line for a respective bidirectional data transfer between the data connection and the first and second local data lines;
an output circuit for performing a read access to the two cell groups, the output circuit being located adjacent to the data connection;
the first and second global data lines being connected to the data connection via the output circuit, the output circuit having two operating states for feeding two items of data respectively provided on the first and second global data lines to the data connection in a respective different order;
an input circuit for performing a write access to the two cell groups, the input circuit being located adjacent to the two cell groups;
a receiving unit located at the data connection;
the data connection being connected to the first and second global data lines via the receiving unit, the data connection, in the event of the write access to the two cell groups, being fed a first datum and subsequently a second datum, the receiving unit, in the event of the write access, feeding the first datum to the first global data line and feeding the second datum to the second global data line; and
the first and second global data lines being connected to the first and second local data lines via the input circuit, the input circuit having two operating states for feeding the first datum and the second datum in a respectively different assignment to the first and second local data lines.
According to the invention, it is provided that although the output circuit, which, in the event of a read access to the memory, outputs the data read from the two cell groups in the correct order at the data connection, is provided adjacent to the data connection, the input circuit, which, in the event of a write access to the memory, assigns the two items of data arriving successively at the data connection to the respectively correct cell group, is however provided adjacent to the two cell groups. For this purpose, the first datum arriving first at the data connection is, in principle, fed via the first global data line and the subsequently arriving, second datum is fed via the second global data line to the input circuit.
Due to the input circuit not being provided adjacent to the data connection but adjacent to the two cell groups, there is a longer period of time available for the decision as to which datum is to be fed to which cell group than in conventional memories. This is due on the one hand to the fact that the data fed to the data connection in the event of a write access firstly propagate through the entire length of the global data lines before they reach the input circuit, in which the decision for the assignment is made. On the other hand, by virtue of the input circuit not being provided at the data connections, which are usually provided peripherally at the edge of the memory, but rather being provided at the cell groups, which are usually provided closer to the center of the chip, the line length for a control signal which controls the assignment is shortened, with the result that the line propagation delay of the control signal until the control signal reaches the input circuit is shorter than in conventional memories. Consequently, such a control signal arrives faster or earlier at the input circuit, whereas the data to be written arrive there later, than in conventional memory devices. Therefore, there is more time available for the assignment of the data to be written to the two cell groups than in known memory devices, with the result that undesirable waiting times with regard to the assignment are avoided and the write access can be effected without corresponding waiting times, and hence very rapidly, even in the case of data to be written which arrive at a high frequency.
In accordance with another feature of the invention, a control signal is provided, which is fed in each case to a control input of the output circuit and of the input circuit and on which the operating state both of the output circuit and of the input circuit depends.
In accordance with yet another feature of the invention, the memory cells are provided at cross-over points of word lines and bit
Dietrich Stefan
Partsch Torsten
Schrogmeier Peter
Weis Christian
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
LandOfFree
Integrated memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2518044