Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-10-30
2001-09-25
Phan, Trong (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S063000
Reexamination Certificate
active
06295219
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having a cell array with a plurality of memory cells located at intersecting points of associated word and bit lines. A row decoder is provided for addressing the word lines in response to received row address signals. The row decoder has amplifiers for outputting decoder signals onto the word lines.
Such an integrated memory is described in Published, European Patent Application EP 0 428 785 A1, for example, where driver stages for driving the word lines are situated between cell array blocks. The driver stages drive output signals from word decoders.
In the so-called “folded bit line structure” of the prior art, two bit lines of a bit line pair run parallel to one another in a wiring plane of the memory. During memory accesses, the two associated bit lines carry opposite potentials in each case, namely logic 1 and logic 0. The interfering influences caused by the bit lines on the word lines which cross them are at least partly canceled out on account of their opposite potentials. A so-called “vertical folded bit line structure” is conceived of, inter alia, for future memories. In this structure, the two bit lines of a bit line pair do not run in a common wiring plane of the memory but rather above one another in different wiring planes. Therefore, compensation of the interfering influences—caused because of capacitive coupling—on the word lines which cross the bit lines no longer occurs in such memories. In memories of this type, therefore, the signals present on the word lines could be subjected to interference in an impermissible manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which any impairment caused by the interfering influences is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory having word lines formed of first and second conductive structures disposed in each case in different wiring planes. Each of the first conductive structures is embodied substantially in one piece. Each of the second conductive structures have a plurality of segments embodied such that they are separated from one another by interruptions and each of the segments is connected to an associated one of the first conductive structures. Bit lines are provided that cross over the word lines at crossover points. A cell array having a plurality of memory cells disposed at the crossover points of the word lines and the bit lines is provided. Each of the memory cells have a selection element for selection of a respective memory cell of the memory cells, the selection element having a control terminal connected to one of the word lines. A row decoder is provided and has outputs connected to one end of the word lines at an edge of the cell array and inputs receiving row addresses. The row decoder, in a manner dependent on the row addresses generates decoders signals driving the word lines. The row decoder has an output side and first amplifier units disposed on the output side for driving the decoder signals onto the word lines. Second amplifier units are disposed within the cell array. At least one of the second amplifier units is provided for each of the word lines for amplifying the decoder signals driven onto the word lines by the first amplifier units. The second amplifier units are disposed in the interruptions between the segments of associated ones of the second conductive structures and are connected to the first conductive structures for amplifying the decoder signals propagating on the first conductive structures.
According to the invention, at least one additional second amplifier unit is provided per word line for amplifying the decoder signals driven onto the word lines by the first amplifier units, which unit is disposed within the cell array and is connected to the associated word line.
The second amplifier units thus locally amplify in the cell array the decoder signals that are fed to them. The additional amplification of the decoder signals prevents the latter from being influenced by interfering influences which may be caused for example by crosstalk on account of signal changes occurring on the bit lines.
It is particularly advantageous if the second amplifier units are holding circuits that amplify the decoder signals fed to them but are not disposed in the signal path which is to be traveled by the decoder signals and is formed by the respective word line. This prevents the occurrence of a propagation delay of the decoder signals on the word lines on account of the presence of the second amplifier units.
By way of example, the second amplifier units may be disposed at that end of the associated word line that is remote from the associated first amplifier unit. This has the advantage that the decoder signals propagating on the word lines are amplified at the point where they are the weakest, since that is where the distance from the first amplifier units is the greatest.
In accordance with another feature of the invention, the first conductive structures are formed from metal and the second conductive structures are formed from polysilicon.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 6157561 (2000-12-01), Schlager et al.
patent: 196 14 561 C2 (1999-03-01), None
patent: 0 019 241 A1 (1980-11-01), None
patent: 0 428 785 A1 (1991-05-01), None
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Phan Trong
Stemer Werner H.
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