Integrated memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Patent

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Details

36523003, 365200, 365 63, G11C 800

Patent

active

060288159

ABSTRACT:
The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.

REFERENCES:
patent: 4888736 (1989-12-01), Hasimoto et al.
patent: 5539696 (1996-07-01), Patel
patent: 5636174 (1997-06-01), Rao
patent: 5654932 (1997-08-01), Rao

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