Integrated magnetic buck converter with magnetically coupled...

Details Integrated magnetic buck converter with magnetically coupled... Integrated magnetic buck converter with magnetically coupled...

2002-09-17

2004-06-22

Pert, Evan (Department: 2827)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S018000, C327S540000

Reexamination Certificate

active

06754086

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a power conversion methodology and circuit for a tapped-inductor buck topology that in general relates to systems and methods for power conversion, and in particular to a system and method for power conversion that takes advantage of an integrated magnetic auxiliary reset winding and intrinsic leakage inductance in the coupled inductors of a tapped-inductor buck converter to reuse the energy in the circuit to help power a simple MOSFET lower switch gate-drive circuit which improves the overall efficiency of the converter, while simultaneously simplifying the circuit design in multiphase power conversion for voltage regulation (VR) technologies.
2. Description of the Related Art
High performance electronics today are demanding higher performance power delivery than in previous years. As an example, high performance microprocessors are forcing power converters to supply voltages at 1 Volt (V) and below and deliver power over 100 Watts (W). This translates to delivered currents in excess of 100 amps. Moreover, the small space allocated on motherboards and other printed circuit boards, along with the thermal considerations at the system level, require the voltage regulators to be highly efficient, have low noise, and maintain a very small form factor. This trend is requiring advancements in power conversion technology which not only necessitate using advanced componentry but sophisticated topologies and circuit design in power conversion as well.
Today, input voltages for many non-isolated power converter technologies in high performance microelectronics is 12V (though 48V input voltages are becoming more common as well). Use of lower input voltages than 12V increases conduction loss and is used less frequently. Use of higher input voltages often results in more complex power distribution and is typically more costly. As an example, 48V input converters usually require the addition of a 48V to 12V first stage converter followed by a second stage 12V to low voltage (e.g. 1V to 2V) converter to optimize the efficiency and performance of the field effect transistors (FETs) typically used in such circuits. To maximize efficiency, space, and cost, most non-isolated DC-to-DC converters today are based upon the simple Buck topology.
FIG. 1
shows a schematic of a buck converter circuit
100
. The buck converter circuit
100
has a first main switch
104
coupled to an input signal
102
and a second main switch
106
. Typically, the first and second main switches
104
and
106
are field effect transistors (FETs) such as metal oxide field effect transistors (MOSFETs), each having gates
114
and
116
, respectively. As illustrated in
FIG. 1
, the switches
104
and
106
can be individual switches or can be combined in a single device. In combination with the other circuit elements illustrated, the switches are used to step down the higher 12V input to a lower voltage—typically below 2V.
An inductor
108
is connected between the output V
out
112
and the junction of the two switches
104
and
106
(labeled “A” in FIG.
1
). The drain of the first (upper) switch
104
is electrically connected to V
in
102
, which is typically 12 volts, while the source of the lower switch
106
is electrically connected to ground
122
with one end of the inductor
108
between them. The output
112
includes a capacitor
110
connected between inductor
108
and ground
122
for storage of charge and filtering. A load (not shown) is connected to the output
112
where power is delivered.
FIG. 2
is a timing diagram further illustrating the operation of buck converter
100
. When the upper switch
104
is on (V
G104
at time t
1
to t
2
), the gate voltage
116
on lower switch
106
(V
G106
at time t
1
to t
2
) is at a low voltage, turning off lower switch
106
. Because the upper FET
104
is on, the voltage at node A is high (V
A
at time t
1
). A controller (not shown) drives the two switches
104
and
106
. The control of switches
104
and
106
is timed so that each switch is (ideally) off when the other switch is on. However, FET switches
104
,
106
cannot turn on and off instantaneously in a perfectly timed manner. Additionally, parasitic effects of the FET switches
104
,
106
, such as the substrate diode and the drain-to-source capacitance, contribute to the non-ideal switching. What occurs is the substrate diode of the lower switch is brought into conduction due to the upper transistor switch not instantaneously responding to the inductor current with the lower switch turned off. Because of these problems, large voltage and current spikes occur across the FET switches
104
and
106
, particularly the upper FET switch
104
, which results in increased losses through the FETs
104
and
106
[P
104/106
from t
1
to t
2
] and can cause potential damage to the FETs themselves. Also occurring at time t
1
, the current through upper FET
104
spikes [I
S104
at time t
1
] due to the substrate diode of lower FET
106
continuing to conduct even after the gate voltage
116
of FET
106
is low (e.g. the FET is turned off). This surge current continues until the substrate diode of FET
106
is completely off. The current through upper FET
104
then increases until time t
2
when the gate voltage [V
G104
at time t
2
] goes low and another power spike occurs at time t
2
. During the on cycle of the upper FET
104
power is being delivered to the output. This can be seen by noticing the inductor current I
108
increases until time t
2
when upper FET switch
104
is turned off. During the conduction cycle of the lower FET
106
, current continues to flow through inductor
108
from time t
2
to time t
3
. The cycle repeats itself starting at time t
3
.
The asymmetric behavior of the current through inductor
108
in a buck converter results in a large ripple voltage, which may not be conducive to proper electronic device operation. Thus, to mitigate this problem, designers typically use multiple phases of the buck topology to reduce output voltage ripple and current through each FET. A multi-phase buck converter has two or more converters, similar to buck converter
100
, operating synchronously through a main controller circuit to deliver power to a common load. Multi-phase operation helps reduce output voltage ripple while sharing the current equally through each phase of the converter.
Though the buck converter
100
is simple and elegant it has its drawbacks for high current low voltage power delivery. The duty cycle for the buck converter is small and may be approximated by the relation D≈Vo/Vin, resulting in very short on times for the upper FET switch
104
as illustrated above. Because of this short duty cycle the rising and falling inductor currents are asymmetric resulting in poor transient response. This is because the declining rate of change of current of the inductor
108
is slow relative to the rising speed. Additionally, the turn-off current for the upper FET switch
104
is equivalent to the peak output current, which results in very high losses in the upper FET during the switching, cycles (e.g. when the upper FET switch is on). Some of these problems may be mitigated through modifications of the standard buck topology as will be shown.
FIG. 3
is a diagram showing another converter topology known as a tapped-inductor buck converter
300
. The tapped-inductor buck converter
300
uses a coupled input inductor
304
and output inductor
310
between the upper FET
306
and the input voltage source
302
with the inductors coupling magnetically to each other. Throughout this description coupled inductors will be shown with the dot convention . . . one type of dot will show coupling between one set of coupling, etc. Instead of the drain of the upper FET
306
connecting to the input voltage
302
the input inductor
304
is connected between it and the input
302
. As shown in
FIG. 3
, tapped-inductor buck converter circuit
300
has input voltage source VIN
3

Affiliated with

Also associated with

Rating

Integrated magnetic buck converter with magnetically coupled... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated magnetic buck converter with magnetically coupled..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated magnetic buck converter with magnetically coupled... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3365352