Integrated low ripple, high frequency power efficient...

Details Integrated low ripple, high frequency power efficient... Integrated low ripple, high frequency power efficient...

2001-06-18

2003-09-30

Berhane, Adolf D. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

06628109

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to electrical circuits, and more particularly to a circuit and method of generating a hysteretic controller circuit having improved power efficiency at low load currents by making the natural frequency associated therewith a function of the circuit load current.
BACKGROUND OF THE INVENTION
Switching power supply circuits are utilized in a number of different circuit applications. The three basic switching power supply topologies in common use are the buck, boost and buck-boost type power stages. These topologies are non-isolated, that is, the input and output voltages share a common ground. There are, however, isolated derivations of these non-isolated topologies. The differing topologies refer to how the switches, output inductor and output capacitor associated therewith are interconnected. Each topology has unique properties which include the steady-state voltage conversion ratios, the nature of the input and output currents, and the character of the output voltage ripple. Another important property is the frequency response of the duty cycle-to-output voltage transfer function.
The most common power stage topology is the buck power stage, sometimes called a buck converter or a step-down power stage (because the output is always less than the input). The input current for a buck power stage is said to be discontinuous or pulsating if a switching current pulses from zero or some negative value to some positive output current value every switching cycle. The output current for a buck power stage is said to be continuous or nonpulsating because the output current is supplied by an output inductor/capacitor combination. In the latter event, the inductor current never reaches a zero or negative value.
An exemplary basic buck converter circuit is illustrated in prior art
FIG. 1
a
, and designated at reference numeral
10
. When a power switch
12
is activated, the switch behaves like a closed circuit, as illustrated in prior art
FIG. 1
b
, and the input voltage V
IN
is applied to an inductor
14
, and power is delivered to an output load
16
. The output load voltage is V
OUT
=V
IN
−V
L
, wherein the V
L
, the voltage across the inductor
14
, is given by L(di/dt). The output voltage V
OUT
also is formed across a capacitor
18
, thus the capacitor charges and the output voltage increases each time the switch
12
is closed.
When the switch
12
is deactivated, or turned off, the switch
12
behaves as an open circuit, as illustrated in prior art
FIG. 1
c
, and the voltage across the inductor
14
reverses due to inductive flyback, thus making a circuit diode
20
forward biased. The circuit loop generated by the diode
20
allows the energy stored in the inductor
14
to be delivered to the output load
16
, wherein the output current is smoothed by the capacitor
18
. Typical waveforms for a buck converter are shown in FIG.
2
. The power switch
12
is switched at a relatively high frequency (e.g., between about 20 KHz and about 300 KHz for most converters) to produce a chopped output voltage, however, the inductor
14
and capacitor
18
together operate as an LC filter to produce a relatively smooth output voltage having a DC component with a small ripple voltage overlying the DC value (see, e.g., output voltage waveform of FIG.
2
). The ripple voltage can be controlled by varying the duty cycle of the power switch control voltage.
The base principle of operation in the above buck converter
10
is often utilized in hysteretic dc—dc converters, as illustrated in prior art
FIG. 3
, and designated at reference numeral
30
. The circuit
30
is similar in various respects to the buck converter
10
of
FIG. 1
a
and employs a unity gain buffer
32
serially coupled to an analog comparator circuit
34
having a hysteresis V
H
. The comparator
34
compares the input reference voltage V
REF
to the circuit output voltage V
OUT
and provides an output signal at node
36
which is a function of the comparison and constitutes a generally square wave. An exemplary output voltage waveform for the circuit
30
is illustrated in FIG.
4
.
The hysteresis V
H
of the comparator
34
impacts the operation of the circuit
30
in the following manner. As the output V
OUT
falls below a voltage V
REF
−V
H
, the comparator
34
trips and the output thereof at node
36
goes from zero to the supply, ideally, which then is fed to the circuit output V
OUT
(wherein, V
OUT
is a function of the output of the comparator and the duty cycle of the driver). Similarly, as V
OUT
increases to a voltage V
OUT
+V
H
, the comparator
34
again trips and the output thereof at node
36
decreases to zero volts, which is fed to the circuit output V
OUT
. Therefore the hysteresis V
H
of the comparator
34
dictates an amount of voltage ripple (2*V
H
) about the target reference voltage V
REF
, as illustrated in
FIG. 4
, and, in conjunction with the output capacitor dictates a natural frequency of the ripple voltage at the output V
OUT
.
In many applications it is desirable to increase the natural frequency of the circuit
30
since a higher frequency allows use of a smaller capacitor, provides a smaller output ripple voltage, and provides a faster circuit response time. One conventional way of decreasing the natural frequency of a hysteretic dc—dc converter is to decrease the hysteretic window of the comparator
34
. That is, instead of using a hysteretic value of V
H
, a smaller value (e.g., V
H
−&Dgr;V
H
) is used. With a smaller hysteretic window, the comparator
34
trips earlier, thus increasing the natural frequency. While decreasing the hysteretic window in systems employing relatively large ripple voltages (e.g., on the order of about 100 mV or more) is a viable solution, such an approach is not practical in systems employing smaller ripple voltages (e.g., on the order of about 50 mV or less) because in such systems it becomes difficult to generate a well-controlled hysteresis window that is small and simultaneously insensitive to noise and random offset voltages. In other words, the accuracy requirements of the hysteretic comparator are generally more stringent for lower ripple voltages.
Therefore there is a need in the art for a circuit and method of providing an increased natural frequency in hysteretic circuits without altering the hysteretic window associated therewith.
SUMMARY OF THE INVENTION
According to the present invention, a circuit and method of altering the natural frequency of a hysteretic circuit as a function of load current is disclosed.
The present invention varies the natural frequency of a hysteretic dc—dc converter circuit as a function of the converter load current. The present invention generates and couples an AC ramp signal to the input reference voltage. The AC ramp signal preferably is an inverted version of the feedback output voltage used as the sense node in conventional circuit. The AC ramp signal has a slope which is a function of the circuit load current and is used to vary a natural frequency of the converter circuit as a function of the converter circuit load current. For example, the slope of the ramp signal is decreased as the load current decreases. The decreased ramp signal slope decreases the trip frequency of a comparator circuit which decreases the natural frequency of the converter circuit, thereby lowering switching losses associated therewith and improving the power efficiency at low load currents.
According to one aspect of the present invention, a hysteretic dc—dc converter circuit includes a feedback circuit in addition to the traditional feedback for altering a natural frequency of the converter. The feedback circuit includes positive and negative ramp current source circuits which are utilized to charge and discharge a ramp capacitor at rates which are a function of the load current. The ramp capacitor voltage is then used as the ramp signal to alter a trip frequency of a comparator circuit within the converter which results in an adjustment of the natural fr

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