Integrated logic gate with NPN inverter, PNP clamp, coupling, Sh

Details Integrated logic gate with NPN inverter, PNP clamp, coupling, Sh Integrated logic gate with NPN inverter, PNP clamp, coupling, Sh

1979-03-14

1981-09-08

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307458, 357 15, 357 46, 357 48, 357 92, H01L 2704, H03K 19084, H03K 19091

Patent

active

042888050

ABSTRACT:
A logic element structure suitable for high density integration including a vertical NPN transistor, a lateral PNP anti-saturation transistor, and a Schottky diode coupled to the collector of the NPN transistor and providing a logic element output. The logic element structure is fabricated as a monolithic integration on a semiconductor crystal and comprises an isolated region of N-type semiconductor material bounded on its inner principal face by a substrate and by a buried layer of N.sup.+ type material, the isolated region being further bounded on its lateral faces by an insulating wall of P-type semiconductor material and on its principal outer face by a first region of P-type semiconductor material, this first region of P-type semiconductor material at the periphery of the isolated region and partially covering the insulating wall, the isolated region being further bounded on its principal outer face by a second region of P-type semiconductor material insulated from the first region of P-type semiconductor material by a minimum thickness of N-type semiconductor material, this second region of P-type semiconductor material surrounding a second region of N.sup.+ -type semiconductor material, the Schottky diode formed by a metallization on the principal outer face of the isolated region between the first and second P-type semiconductor regions.

REFERENCES:
Lohstroh, IEEE J. of Solid-State Circuits, vol. SC 14, No. 3, Jun. 1979, pp. 585-590.
Berger et al., IBM Technical Disclosure Bulletin, vol. 20, No. 2, Jul. 1977, pp. 636-637.
Porter, IEEE J. of Solid State Circuits, vol. SC 12, No. 5, Oct. 1977, pp. 440-449.
Peltier, IEEE International Solid State Circuits Conf., Feb. 14, 1975, Digest of Technical Papers, pp. 168-169.
Electronics, Jun. 8, 1978, pp. 41-42.
Berger et al., "Merged Transistor Logic . . . ", IEEE J. of Solid-State Circuits, vol. SC 7, No. 5, Oct. 1972, pp. 340-346.

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