Integrated logic circuit with clock skew adjusters

Details Integrated logic circuit with clock skew adjusters Integrated logic circuit with clock skew adjusters

1989-10-13

1992-06-16

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 328 63, 328 72, 328155, H03K 513, H03K 301

Patent

active

051226790

ABSTRACT:
In an integrated logic curcuit, a plurality of clock skew adjustors generate clocks having coincident phases in reaponse to frequency information and phase information fed from a clock source. These clock source and clock adjustors are arranged so that their individual signal delays may be substantially equalized.

REFERENCES:
patent: 4309649 (1982-01-01), Naito
patent: 4495473 (1985-01-01), Treise
Anceau, "A Synchronous Approach for Clocking VLSI Systems", IEEE SSC, vol. SC-17, No. 1, Feb. 1982.
NEC Technical Report, Aug. 1983, "Ultrahigh-Speed ECL Gate Array Family", pp. 1-12, T. Takahashi et al.

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