Integrated logic circuit having interconnections of various leng

Details Integrated logic circuit having interconnections of various leng Integrated logic circuit having interconnections of various leng

1978-01-09

1980-08-19

Munson, Gene M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 23, 357 45, 357 59, 357 91, 307304, H01L 2702, H01L 2978, H01L 2710, H03K 3353

Patent

active

042186935

ABSTRACT:
An integrated logic circuit includes an array of insulated gate field effect transistors formed at the crossings of a plurality of substantially parallel first conductor tracks which form the transistor gate electrodes and a plurality of substantially parallel strip-shaped surface regions which form the source and drain electrode regions of the transistors. The field effect transistors of the device include a first group of transistors having a first threshold voltage and a second group of transistors having a second threshold voltage different from the first. In order to make a more compact, easily-designed and easily-manufactured circuit, the conductor tracks and the strip-shaped surface regions form a nonuniform array in which the track and surface regions need not all be of the same length. Further efficiencies are achieved by branching the strip-shaped surface regions where appropriate to implement the desired logic combination.

REFERENCES:
patent: 4037242 (1977-07-01), Gosney
patent: 4085498 (1978-04-01), Rideout
patent: 4107548 (1978-08-01), Sakaba et al.
patent: 4110776 (1978-08-01), Rao et al.
patent: 4125854 (1978-11-01), McKenny et al.
Kawagoe et al "Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI" IEEE J. Solid-State Circuits vol. SC-11 (6/76) pp. 360-364.

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