Integrated logic circuit having collector node with pull-up and

Details Integrated logic circuit having collector node with pull-up and Integrated logic circuit having collector node with pull-up and

1983-06-09

1986-03-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307458, 307459, 307551, 307559, 307303, 357 92, H03K 19013, H03K 19091, H03K 508, H01L 2970

Patent

active

045771235

ABSTRACT:
A logic circuit of the I.sup.2 L, the ISL or the STL type having a signal input formed by the control electrode of an inverter transistor and plural signal outputs each coupled through a diode to a main electrode of the inverter transistor, this main electrode being connected to a supply line through a pull-up connection. The improvement relates to a further connection path comprising a Schottky diode and a resistor which bridges the main current path of the inverter transistor and which reduces the voltage swing at the main electrode.

REFERENCES:
patent: 3987310 (1976-10-01), Peltier et al.
patent: 4239981 (1980-12-01), Crookshanks
patent: 4288805 (1981-09-01), Depey
patent: 4317127 (1982-02-01), Nishizawa
patent: 4450468 (1984-05-01), Nishizawa et al.
Lohstroh et al., "Propagation Delay Times of ISL and STL"; IEEE JSSC, vol. SC-17, No. 4, pp. 687-695; 8/1982.
Lohstroh et al., "Temperature Behavior of the Voltage Swings and the Static Noise Margins of ISL and STL"; IEEE-JSSC, vol. SC-17, No. 4, pp. 677-686; 8/1982.
Bursky, "ISL Array Packs Nearly 1200 Gates Yet Handles 40-MHz Clocks"; Electronic Design, p. 131; 9/1/1979.

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