Integrated line selection apparatus within active matrix arrays

Details Integrated line selection apparatus within active matrix arrays Integrated line selection apparatus within active matrix arrays

2006-10-30

2010-10-19

Shalwala, Bipin (Department: 2629)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

Reexamination Certificate

active

07817129

ABSTRACT:
An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

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N. Mohan et al., “Stability Issues in Digital Circuits in Amorphous Silicon Technology,” Proceedings from IEEE CCECE, 2001, pp. 583-588, vol. 1, Toronto, Canada.
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