Integrated inrush current limiter circuit and method

Details Integrated inrush current limiter circuit and method Integrated inrush current limiter circuit and method

2005-03-08

2005-03-08

Leja, Ronald (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

C361S058000

Reexamination Certificate

active

06865063

ABSTRACT:
An inrush current limiter circuit (20) includes a mirrored transistor (50) responsive to a control signal (VDRIVE) developed from a sense current (ISENSE), and has a first source (51) coupled to a supply voltage, a common drain (53) that routes a load current (ILOAD) to an output node (45), and a second source that samples the load current to produce the sense current. A fault protection circuit (64) disables the mirrored transistor in response to a first fault condition (TEMP, UVLO) and is coupled to a first lead (43) for externally adjusting a fault threshold. A fault communication circuit (250) is coupled to the first lead to receive a fault signal representative of an external fault condition to disable the mirrored transistor.

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patent: 20020166073 (2002-11-01), Nguyen et al.

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