Integrated injection logic output circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307475, 307477, 357 92, H03K 19091, H03K 19092

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active

047407204

ABSTRACT:
An I.sup.2 L output circuit is described for supplying current (I.sub.D ') to an output node (8) of a plurality of I.sup.2 L blocks (7) in order to ascertain the logic condition at the output node. The output circuit includes a standard I.sup.2 L gate (11) with an input connection (12) to the semiconductor region comprising both the lateral injector transistor collector electrode and the vertical switching transistor base electrode, and an output connection (13) from the semiconductor region comprising one of the collectors electrodes of the switching transistor. The gate output being used to control two identical current sources (T.sub.11, T.sub.12) one of which (T.sub.11) supplies current to the input of a simple current mirror (T.sub.13, T.sub.14) having its output connected to the gate input. The other current source (T.sub.12) being connected to the output node of the logic blocks. The provision of a current feedback loop around the I.sup.2 L gate in this way ensures that, upon stabilization, the current (I.sub.D ') from the current source into the output node is very close in value to the internal injector current (I.sub.J) of the I.sup.2 L gate.

REFERENCES:
patent: 3736477 (1973-05-01), Berger
patent: 3956641 (1976-05-01), Berger
patent: 4137465 (1979-01-01), Hart
patent: 4158782 (1979-06-01), Price, Jr.
patent: 4204130 (1980-05-01), Harris
patent: 4330853 (1982-05-01), Heimeier
patent: 4348600 (1982-09-01), Jarrett et al.
patent: 4356414 (1982-10-01), Guntner et al.
patent: 4357548 (1982-11-01), Preslar
patent: 4390802 (1983-06-01), Woltz
patent: 4439695 (1984-03-01), Pelletier et al.
patent: 4459496 (1984-07-01), Yamada et al.
Kaneko et al, "Stacked I.sup.2 L Circuit",IEEE JSSC, Apr. 1977, pp. 210-212.

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