Integrated injection logic circuit having reduced delay

Details Integrated injection logic circuit having reduced delay Integrated injection logic circuit having reduced delay

Filed on

1976-12-20

Date issued

1978-04-18

Examiner

Heyman, John S.

Patent Class

Electrical transmission or interconnection systems

SubClass

Nonlinear reactor systems

SubSubClass

Parametrons

Other Related Categories

307208, 307279, 307299B, 307213, H03K 1908

Type

Patent

Status

active

Patent number

040853411

Description

ABSTRACT:
An integrated injection logic storage element having a minimum delay time. Means for steering input data into the circuit are provided. These means are coupled to another means for selectively gating the input data through the circuit. The means for selectively gating is responsive to a clock pulse. A third means for providing an output storage latch and having multiple outputs is coupled to the means for selectively gating. At least one of the multiple outputs is coupled to an output of the means for selectively gating thereby providing an output which has a delay time which is less than another one of the multiple outputs which is not coupled to the means for selectively gating.

REFERENCES:
patent: 3673434 (1972-06-01), McIntosh
patent: 3947697 (1976-03-01), Archer et al.
patent: 3976949 (1976-08-01), Hepworth et al.
patent: 3993918 (1976-11-01), Sinclair

Affiliated with

Also associated with

Rating

Integrated injection logic circuit having reduced delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated injection logic circuit having reduced delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated injection logic circuit having reduced delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2148553