Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1997-09-18
2001-12-04
Henderson, Christopher (Department: 1713)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S700000, C438S704000, C438S733000, C438S745000, C438S756000, C438S739000, C438S753000, C216S002000
Reexamination Certificate
active
06326314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to the field of integrated circuits (ICs) used in radio frequency (RF) and microwave circuits, and in particular, to the construction and integration of inductors within such ICs.
2. Description of the Related Art
Electrical systems are made up of various components, including active elements such as transistors, and passive elements such as inductors, capacitors, and resistors.
One common electrical system is a phase-locked loop (PLL). A PLL is a frequency-selective system that uses feedback to maintain an output signal in a specific phase relationship with a reference signal. Monolithic PLLs are used in many areas of electronics to control the frequency and/or phase of a signal. These applications include FM detectors, frequency synthesizers, and analog and digital modulators and demodulators.
FIG. 1
shows the block diagram of a basic phase-locked loop system
100
which comprises a phase detector
101
, a voltage-controlled oscillator (VCO)
103
, and a loop filter
105
. The PLL
100
operates such that the phase detector
101
compares two input frequencies, f
in
and f
vco
, and generates an output that is proportional to their phase difference. If the two input frequencies are not equal, the VCO
103
generates an output signal which shifts in frequency in the direction of f
in
. If the input frequencies are equal, then the VCO “locks” to the input frequency maintaining a fixed phase relationship with the input signal. The loop filter
105
controls the PLL dynamics and therefore the performance of the system.
A key component of the PLL is the voltage controlled oscillator (VCO) which tracks the incoming signal or extracts information from it. An important design aspect of the VCO is the noise content of the output signal. The dominant resultant noise will appear as phase noise (jitter) on the output signal from the VCO. Due to the dynamics of the PLL some of the sources of noise will be filtered by the loop functions that have either a low-pass characteristic or a high-pass characteristic. Typically it will be found that one particular noise source will be dominant and the PLL performance can then be adjusted to minimize the output noise.
A PLL is frequently used to enhance the noise performance of an oscillator by taking advantage of these noise-filtering properties. For example, a crystal oscillator typically has very good low frequency noise characteristics and integrated inductive-capacitive (LC) oscillators can substantially reduce phase jitter of a complementary metal oxide semiconductor (CMOS) IC VCO. Indeed this integrated LC oscillator is desirable because it operates at the limits of CMOS performance levels, and because feedback techniques typically are not fast enough.
The problem with the conventional integrated LC oscillators is that power levels are too high due to current shoot-through in the inductor which results from a very low inductance quality value, Q. Additionally, the temperature dependence of the oscillation frequency is too great for practical operation of the integrated LC oscillator in VCO designs.
These intrinsic problems stem from the interaction of the inductor with the substrate on the wafer. The substrate absorbs a significant amount of RF energy radiated from the inductor which reduces the inductance quality value, Q. Additionally, the self-resonance caused by the parasitic capacitance of the inductors to the substrate reduces the maximum effective operating frequency, Fmax. Each of these effects decreases the overall performance of an integrated LC oscillator.
These problems caused by the interaction with a substrate can be overcome by making the area under the inductor appear locally insulating. By etching out the substrate from under the inductor such that the inductor is encased in a suspended oxide layer attached to the rest of the silicon wafer, the interaction between the inductor and the substrate is minimized. This technique of suspending the inductor in the air over the etch pit, is further explained in Large Suspended Inductors on Silicon and Their Use in a 2-um CMOS RF Amplifier, IEEE Electron Device Letters, Vol. 14, No. 5, May 1993, pp.246-48, and A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver, IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, July 1996, pp. 880-89, both of which are incorporated herein by reference.
Page 883 of the latter publication describes a method of eliminating the parasitic capacitance under a spiral inductor by selectively removing the underlying silicon substrate. This leaves the spiral encased in a layer of oxide suspended above an air-gap gap. Via holes which will expose the surface of the silicon after fabrication and passivation surround the spiral. A selective etchant removes the exposed silicon at a much higher rate than it does oxide and metal. After sufficient exposure to the etchant, a deep cavity forms under the inductor, while the remaining active area is left intact.
Such a suspended inductor technique does permit wholly-integrated RF components in CMOS circuits. Thus, the suspended inductor is useful in a local oscillator, a low-noise-amplifier, a power amplifier, and even a low quality bandpass filter. However, since the wafer on which the suspended inductor is fabricated is very fragile, it easily susceptible to breaking. Due to this susceptibility, the suspended inductor is not a robust architecture for the typical plastic package assembly process. The plastic package process typically involves injecting an epoxy compound under pressure into the cavity under the suspended inductor, as a result, if the inductors are not sufficiently supported they can be damaged during the package process. Thus, a need exists to achieve performance equivalent to that of a suspended inductor, while simultaneously achieving a more rugged structure.
SUMMARY OF INVENTION
An integrated inductor fabricated on a wafer and having a robust architecture and reduced substrate interaction is achieved by forming an inductor on the substrate. The inductor is then etched to form an opening in a portion of the inductor to expose the substrate. The exposed substrate is then etched to form an isolation pit beneath the inductor. The isolation pit will etch in an inverted pyramidal shape. Subsequently, the isolation pit is filled with a material, such as spin-on-glass. As a result, an inductor having a rugged architecture is therefore constructed.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
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Lee Tsung-Wen
Merrill Richard Billings
Henderson Christopher
National Semiconductor Corporation
Stallman & Pollock LLP
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