Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-12-11
2003-09-02
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S010000, C336S200000, C336S225000
Reexamination Certificate
active
06614093
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field of semiconductor manufacture, and particularly to fabricating an inductor in a semiconductor device.
BACKGROUND OF THE INVENTION
Semiconductor manufacture has long been able to create component parts on a micron scale. In semiconductor manufacture, various layers of conductive material, dielectric material, and semiconducting material are deposited and etched to form structures on silicon, ceramic, plastic, or other substrates. The processing includes laying down resist materials and etching those materials through masks. Thin film FET transistors, consisting of drain, gate, and source terminals, may be constructed through the deposition and etch processes. Capacitors may also be constructed by the processing. Diodes may also be formed on the substrate.
There are several processes for forming integrated circuit layers on a substrate.
The CVD process involves masking the surface of a semiconducting substrate with an oxide or nitride and removing the oxide or nitride in the areas where epitaxial growth is desired. In CVD, all reactants required for film growth are simultaneously exposed to a wafer surface, where they continuously deposit a thin film. CVD deposition rates can be surface-limited at lower temperatures, or mass-flow-limited at higher temperatures where deposition rates are relatively higher. Layers are deposited. A photoresist pattern is then deposited. A mask is placed above the substrate. Portions of the photoresist are developed corresponding to the mask pattern. Etching of the photoresist and underlying layer occurs. The photoresist is removed to yield a desired pattern. A planar structure is achieved by etching holes to interconnect various layers. Epitaxial growth by CVD requires a surface catalyzed reaction. Deposition occurs only on the semiconducting substrate and not on the oxide or nitride film.
Molecular beam epitaxy (MBE) forms thin films of metal, dielectric, and semiconductor compounds of controllable thickness and conductivity type on a semiconductor substrate. The substrate is first heated to reduce contamination on the surface where the films are to be deposited. A vacuum chamber houses gun port containing several guns thermally insulated from one another. A substrate holder of a refractory material rotates. The substrate holder is provided with an internal heater. A thermocouple is disposed in an aperture on the side of substrate. The chamber includes a pump for evacuating the chamber to a pressure of around a millionth of a Torr. Source material is placed in the source chamber for vaporization by a heating coil which surrounds the crucible. Selected guns are heated so as to vaporize the contents of the crucible to produce a molecular beam. Vaporization may occur by evaporation or sublimation depending on whether the gun temperature is above or below the melting point of the crucible material. Growth of the epitaxial film is done by directing the molecular beam generated by the guns at the substrate surface. Growth is continued for a time period sufficient to yield an epitaxial film of the desired thickness. This technique permits the controlled growth of films of thickness ranging from a single monolayer of several Å to more than 100,000 Å.
Atomic layer deposition (ALD) is a thin-film deposition technique used to fabricate ultrathin and conformal thin film structures below 0.2 &mgr;m. ALD is especially useful for the deposition of ultrathin and conformal films of high dielectric oxides, storage capacitor dielectrics, capacitor electrodes and diffusion barriers. ALD forms layers of oxides, nitrides, metals, and semiconductors to using sequential self-limiting surface reactions to provide atomic layer control and allow conformal films to be deposited on very high aspect ratio structures. In ALD, reactants are introduced in a gaseous state in pulses which are separated from each other by purge gas. Each reactant pulse chemically reacts with the surface of the substrate. When ALD deposits materials to be combined in a single layer, the first reactant may contain the first material and the second reactant the second material. For example, the first pulse may deposit a metal-containing layer, and the second pulse may react with that layer to form the complete film of metal oxide or metal nitride. Film thickness can be controlled to within a monolayer solely by counting pulses. Because ALD has a low deposition rate, it is most suitable for ultrathin films whose thicknesses range from a few to 100 Å. This process makes high quality conformal and uniform films.
Analog circuitry ideally involves the use of both capacitors and inductors as passive components. Capacitors are relatively easy to integrate into integrated circuit manufacturing. Traditionally, inductors have been difficult to manufacture.
Semiconductor manufacturing methods based on the stacked deposition and patterning of successive layers or the lamination of such layers to form high-density wiring structures of sufficient tolerance for inductors have been deficient in that a new layer is fabricated, the previously deposited and patterned layers are exposed to contamination and damage from successive thermal, chemical/solvents, mechanical and other stress-related operations. Defective devices often result. Production is often costly.
Therefore, it would be desirable to provide inductor elements in an integrated circuit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an inductor which is formed on a substrate, especially an integrated circuit substrate.
The present invention can be configured in two different forms. In the first form, inductor coils are constructed parallel to the plane of the substrate, while the core of the inductor extends vertically out of the substrate. This form is the vertically oriented inductor. In the second form, the inductor coils are constructed such that the plane of the coil is perpendicular with the plane of the substrate, while the core of the inductor extends parallel to the plane of the substrate. This form is the horizontally oriented inductor.
In a first aspect of the invention, in the vertical orientation of the inductor, the inductor is formed on a substrate, has a plurality of rings of metallization, wherein each of the rings has a single gap along its perimeter. These rings may be circular or take the form of any polygonal shape. The gap in each successive ring is offset in such a way as to allow a continuous spiral connection.
In a second aspect of the present invention, a method for making a vertically oriented inductor on a substrate, comprises the steps of depositing a first layer of metal on a surface, the first layer of metal having a pattern, depositing a first layer of dielectric material over the first layer of metal having a pattern, forming a first through hole in the first layer of dielectric material, filling the first through hole with a conductive material, and depositing a second layer of metal on the first layer of dielectric material, the second layer of metal having a pattern similar to the pattern of the first layer of metal, with the gap in the pattern offset from the previous layer as described previously.
In a third aspect of the present invention, an electronic circuit on a substrate which includes an inductor formed as part of the substrate, wherein the inductor is formed of a plurality of almost entirely enclosed toroids of conductive material with a non-conductive interior, each toroid having a major plane of extension, wherein each toroid is conductively interconnected with an adjacent toroid by a conductor which extends generally in a plane perpendicular to the major plane of extension of the toroid.
In a fourth aspect of the present invention, a method for forming an inductor whose longitudinal axis is parallel to the major plane of extension of a substrate upon or in which it is formed, including the steps of depositing a first conductive layer and forming first parallel strips of conductive material o
Cole Richard
Ott George
Von Thun Matthew
Eckert George
LSI Logic Corporation
Suiter - West PC LLO
LandOfFree
Integrated inductor in semiconductor manufacturing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated inductor in semiconductor manufacturing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated inductor in semiconductor manufacturing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3012052