Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-11-24
2001-08-14
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S277000
Reexamination Certificate
active
06274920
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated inductor devices; and, more particularly, to an integrated inductor device and a method for fabricating the same, in which a parasitic capacitance and a magnetic coupling can be reduced.
DESCRIPTION OF THE PRIOR ART
Generally, radio frequency integrated circuits (RF ICs) are designed to include an inductor for an impedance matching. The inductance and quality factor of the inductor are decisive factors for determining the performance of the matching circuit. Recently, it is possible to realize an integrated inductor (or, monolithic inductor) which is formed by integrating an inductor on a substrate, and accordingly, many researches into the integration of an active device and a matching circuit are actively underway. The performance of the integrated inductor, especially the quality factor is dependent on a substrate onto which the inductor is integrated and a capacitive coupling which is caused by the parasitic capacitance between the metal line for the inductor and the substrate. Specially, as the parasitic capacitance is increased, the quality factor will be lowered, which leads the result of the deterioration of the RF IC performance. Additionally, the quality factor will be lowered due to a magnetic coupling which is caused by an image current flowing on a lower portion of the substrate.
Currently, if passive devices, e.g., spiral inductors and capacitors, are formed on a gallium arsenide (GaAs) substrate and a silicon substrate in the form of integrated circuit, they can be influenced by the undesirable factors such as the parasitic capacitance and the magnetic coupling. Due to such undesirable factors, the quality factor of the spiral inductor and a self-resonance frequency (ƒ
&ohgr;0
) may be lowered. In order to solve the problem, the influence of the undesirable factors should be reduced.
As one approach for reducing the parasitic capacitance between the substrate and the metal line for the inductor, there has been provided a method for increasing the thickness of a dielectric layer between the metal line for the inductor and the substrate or a method for converting the substrate characteristic has been proposed. Additionally, until now, there are few methods for reducing the magnetic coupling, and it is impossible to measure how much apart the ground plane which can influence the inductor is located from the surface of the substrate. Therefore, it is also impossible to measure how much large area the magnetic coupling can influence.
FIG. 1A
shows a plane view of a conventional inductor device. As shown in
FIG. 1A
, the inductor includes a second metal line
6
which has a square shape and is connected to the first metal line
3
through a via hole
5
.
FIG. 1B
shows a cross-sectional view of the inductor device along the line A-A′ in FIG.
1
A. As can be seen, the conventional inductor includes a first interlayer dielectric layer
2
formed on a silicon substrate
1
. The first metal line
3
is connected to the second metal line
6
for the inductor through the via hole
5
formed in a second interlayer dielectric layer
4
. A reference numeral
7
indicates a passivation layer for protecting the inductor device.
In such a construction shown in
FIGS. 1A and 1B
, the parasitic capacitance is determined by the distance between the substrate
1
and the second metal line
6
, i.e., the thickness of the interlayer dielectric layers
2
and
4
. Since there is a limit to the increase of the thickness, however, it is very difficult to decrease the parasitic capacitance.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an integrated inductor device and a method for fabricating the same, in which a parasitic capacitance and a magnetic coupling can be reduced an integrated device.
In accordance with an aspect of the present invention, there is provided a method for fabricating an inductor device, comprising the steps of: a) forming a plurality of trenches in a substrate by selectively etching the substrate; b) implanting dopants into sidewalls and bottom portion of each trench; c) forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer on a region neighboring to the substrate by diffusing the dopants into the substrate; and d) forming a dielectric layer on the resultant structure to fill the entrance of the trenches, thereby forming air-gap layers in the trenches.
In accordance with another aspect of the present invention, there is provided an integrated inductor device which is formed by integrating an inductor on a substrate, comprising; a trench structure formed in the substrate; a dielectric layer formed on the resultant structure, so that an entrance of the trench structure is filled to thereby form an air gap layer between the trench structure and the dielectric layer; a doped layer formed in a region neighboring to the trench structure; an contact hole for exposing the doped layer; and an electrode, wherein the electrode is connected to the doped layer through the contract hole.
REFERENCES:
patent: 5450263 (1995-09-01), Desaigoudar et al.
patent: 5539241 (1996-07-01), Abidi et al.
patent: 5770509 (1998-06-01), Yu et al.
patent: 5952704 (1999-09-01), Yu et al.
Kim Cheon-Soo
Kim Chung-Hwan
Kim Dae-Yong
Park Min
Yu Hyun-Kyu
Blakely & Sokoloff, Taylor & Zafman
Electronics and Telecommunications Research Institute
Nelms David
Nhu David
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